Design the GPIO with drive strenth calibration function for PVT variation
• General Purpose driver for 3.3V with 1.8V transistor
• Pre driver
• Voltage, current bias circuit Design the Audio Return Channel analog PHY for HDMI 2.1
• Medium speed low level driver with replica circuit
• Input sense amplifier
• Medium speed sampler with clock
- Senior staff analog design engineer at Lattice Semiconductor, INC
- Senior staff analog design engineer at SILICOLN IMAGE, INC
- Senior Design Engineer at LEADIS TECHNOLOGIES, INC
- Staff Design Engineer at SILICON IMAGE, INC
4 years at this Job
- M.S in Electrical Engineering - design
- B.S. in Electronics Engineering - Electronics Engineering
UCC5870 in TI's state of the art IC process: 1. Designed TX monitor. TX monitor is composed of VCC crude, TX supply/bandgap/LDO UV/OVs, Ibias UC/OC and thermal shutdown detector (TSD). When TX VCC exceeds threshold, VCC crude generates VCC OK signal to enable bandgap. UV/OV unit is composed of comparator and resistor ladder with switch for hysteresis. In bandgap UV/OV, voltage reference is buffered by 2-stage opamp with voltage feedback. Ibias UC/OC compares voltage drop of resistors which respectively have two reference current flowing through. LDO OK signal is generated once LDO voltage exceeds bandgap reference voltage. Same low offset comparator is used in all UV/OVs and UC/OC. TSD generates warning/fault signal when PTAT current flowing through resistor exceeds VBE of NPN. 2. Designed TX/RX IO buffers. Input buffers are of Schmitt Trigger structure. Output buffers are designed to achieve good drive strength with small delay. Special care needs to be taken on isolation to prevent latch-up and ESD error. 3. Designed over current protection (OCP) and short circuit protection (SCP). The OCP/SCP functions are triggered once the voltage across the shunt resistor of power switch is higher than pre-defined threshold values. Different thresholds are generated from resistor ladder with trim bits. Comparator contains 3-stage preamp and latch for both low offset and small propagation delay. 4. Designed over temperature protection (OTP). The OTP functions are triggered once the voltage across temperature sensing diode is higher than thresholds. LDO is designed to generate different thresholds from resistor ladder load. Comparator is of low offset and power. 5. Designed Internal TSD for driver. Stacked PNP is used to generate negative TC VBE. PTAT current generation is designed with startup circuit, and VPTAT is created with IPTAT flowing through resistors. Low offset comparator is used to compare VPTAT and VBE, and will toggle TSD output once driver temperature is too high. UCC27792 (Smart Driver) in TI's state of the art IC process: 1. Designed bandgap reference, UVLO and TSD. Bandgap reference operates under 2.5V-20V supply with startup circuit and self-bias reference current for error amplifier. Bandgap voltage is fed to UVLO. In TSD, negative-TC VBE of stacked PNP will compare with bandgap voltage for thermal detection. 2. Designed reference current generator, multi-hundred MHz oscillator and blanking timer. Reference current generator is based on negative voltage feedback V-I structure with high impedance output as current reference. Current reference with magnitude trim is used to charge or discharge cap for both oscillator and blanking timer. 3. Designed HS/LS output sense detector. Compare HS/LS output with voltage reference and level shift the output to low voltage signal for dead time logic circuit. Small propagation delay and low quiescent current is achieved. UCC27524AX (Double Low-Side Gate Driver) in TI's state of the art IC process: Design and verification lead of this double low-side driver spin in low power applications. 1. Output driver: Addressed shoot through issue with achieving complete settle of internal signals; reduced operating current by shrinking width of output transistors; balanced delay in pull-up/pull-down path. 2. LDO: Added high pass filter with switch for better load/line regulation; reduced output PMOS width for lower overshoot; modified miller compensation for speed and less area with good stability. UCC23515, UCC27710/11/12, UCC27780 in TI's state of the art IC process: Design verification lead of UCC23525, UCC27710/11/12 and UCC27780 UCC23515 is single channel isolated gate driver. TX is E-Diode LC oscillator with active clamp. RX is of LANE and driver. Bandpass preamp in LANE achieves amplification with bandpass feature. Envelope detector outputs low/high at low/high frequency input. Anti-shoot-through and Miller clamp technique are used in driver. Completed block level verification on bandgap/LDO/UVLO/LANE/driver. For top level, generated specs results, and completed functional check as CMTI analysis, supply ramp/noise/brownout and input of different patterns.
- Analog Design Engineer at Texas Instruments, Inc
- Analog Design Engineer at Microchip Technology
- Research Assistant at University of Texas at Dallas
2 years, 5 months at this Job
- Master's - Research/Teaching Assistant
- Master's - EE
- Bachelor's - EE
Worked on advanced CMOS nodes like 22nm for LP BGT applications Currently working on the design of LNTA block in the complete receiver chain for mm-wave applications. This LNTA is broadband, low power consumption and linear.
- Senior RF/Analog Design Engineer at Adesto Technologies
- Design Engineer at RFIC
- Characterization Engineer Intern at Lab work
- at Reconfigurable Green Radios Group, IMEC － Leuven
10 months at this Job
- Master of Science in Electrical Engineering - Electrical Engineering
- B.Tech - Electronics & Communication Engineering
- Diploma - Electronics & Communication Engineering
• Implemented a re-configurable activation function for an in-memory computing AI chip.
• Modified the design of the bias generation block of sense amplifier circuit in a NAND flash memory to decrease its size and power consumption.
• Developed a test procedure for the sense amplifier block of a NAND flash memory.
• Wrote R code to perform a statistical data analysis on a DRAM-based ternary-CAM cell performance.
- ANALOG DESIGN ENGINEER at Green Mountain Semiconductor Inc
- GRADUATE RESEARCH/TEACHING ASSISTANT at University of Vermont, Department of Electrical Engineering
- Graduate Research Assistant (GRA) at Missouri University of Science and Technology, Department of Electrical and Computer Engineering
- EMBEDDED SYSTEM ENGINEER at Maharan Eng.
10 months at this Job
- PH.D. IN ELECTRICAL ENGINEERING - Tri-polarized Wireless Channel Characterization for Machine-to-Machine Communication
- M.S. IN COMPUTER ENGINEERING - Leak Detection and Localization
- B.S. IN ELECTRICAL ENGINEERING - Design and Construction of a Simplified CPU for Computer Architecture Laboratory
Design and analysis of critical circuits such as Sense amplifiers and Bandgap reference circuits. Designed a novel Two Phase sense amp which reduces the offset problem at an elevated temperature of 175C. Designed Op-amps, Oscillators and a self-timed delay chain for generating critical timing signals. Design and analysis of read/write paths for non-volatile memories. Analyzing different techniques on operating point analysis, supply noise analysis, EM analysis, mismatch and Monte-Carlo simulations. Modeling in Verilog AMS for an efficient use of design resources and to fasten simulation time. Exposure to UVM Verification Methodology in writing assertions and sequences.
- NVM Analog Design Engineer at NXP Semiconductors
- Graduate Teaching Assistant at Department of Electrical and Computer Engineering, Texas A&M University
- Analog Summer Intern at National Instruments
- at Analog Co-op
3 years, 6 months at this Job
- Master of Science - Electrical Engineering
- Bachelor of Engineering (Honors) - Electronics and Instrumentation
- Sr, Analog Design Engineer at Impinj, Inc.
- Graduate Research Assistant at Georgia Institute of Technology
- Intern at GLOBALFOUNDRIES Inc
- at GLOBALFOUNDRIES Inc
1 year, 8 months at this Job
- Ph.D. - Electrical & Computer Engineering
- M.S - Electrical Engineering
- B.Sc. - (Engg.), Electrical & Electronic Engineering
- Analog Design Engineer at Intel
- Graduate Teaching Assistant at ECEE, Arizona State University, Tempe
- Design Engineer at Qualcomm
2 years, 7 months at this Job
- Masters - Electrical Engineering
- Bachelor of Technology - Electronics and Communication Engineering
Low Jitter Clock buffer for 100G SerDes
- Senior Analog Design Engineer (Contractor) at Wipro
- PRINCIPAL MEMBER TECHNICAL STAFF at Inphi
- PRINCIPAL MEMBER TECHNICAL STAFF at Cortina
- SR. ANALOG DESIGN ENGINEER at STORM
5 months at this Job
- Master of Science in Electrical and Computer Engineering - Electrical and Computer Engineering
- Bachelor of Science in Electronics Engineering - Electronics Engineering
• Responsible is for the design of analog and low voltage power supply boards in the Trip Saver II product. Trip Saver II is a self-powered, electronically controlled single-phase re-closer using vacuum fault interrupter technology. The tasks include: detail circuit design, schematic capture, circuit simulations, analysis, PCB layout supervision, components selection, prototype board debugging, testing, and verification. The analysis includes: part stress analysis, failure mode effects analysis to guarantee reliability over life of 15 years. The tasks also require working well with the different departments at S&C Electric, such as quality assurance, Software Engineering, Mechanical Engineer and purchasing to achieve a design that was cost effective, delivered in timely manner, and met many customer requirements.
• Support qualification testing (ESD, endurance, HALT etc )
• Response for all EMI, FCC compliance.
- Senior Analog Design Engineer at S&C Electric Company
- Senior Analog Design Engineer at Curtiss Wright Corporation
- Senior Analog Design Engineer at Orbital Science Corporation/ Space Systems Group
- Analog Design Engineer at United Technology Corporation
3 years, 8 months at this Job
- Bachelor of Electrical Engineering - Electrical Engineering
• Design of 16 Gbps GMI2 serdes TX in TSMC7 processes
• The half-rate TX includes a 1 UI (62.5 ps) barrel-shifter for 40 TX instance channel alignment, serializer multiplexer chain, multiple test modes including full-rate PRBS-11 checking in intra-TX and loop-back mode. Equalization and ESD capacitance reduction is achieved with t-coils at the transmit pad and unequal source(TX)/termination(RX) resistances. The t-coils were synthesized using Helic tool. Delivered a 7 nm test chip version, and the full product post layout version
• Also supported initial design of 16 Gbps serdes TX in GF14 process, before outside vendor takeover.
- California, U.S.A. - Senior Analog Design Engineer at AMD
- California, U.S.A. - Senior Analog Design Engineer at AMD
- Proficient Design, California, U.S.A. - Principal Analog Design Engineer at GPON
- California, U.S.A. - Senior Analog Design Engineer at KoolChip USA Inc
1 year, 7 months at this Job
- M.S. - Electrical Engineering
- B.E. - Electrical Engineering