• Responsible is for the design of analog and low voltage power supply boards in the Trip Saver II product. Trip Saver II is a self-powered, electronically controlled single-phase re-closer using vacuum fault interrupter technology. The tasks include: detail circuit design, schematic capture, circuit simulations, analysis, PCB layout supervision, components selection, prototype board debugging, testing, and verification. The analysis includes: part stress analysis, failure mode effects analysis to guarantee reliability over life of 15 years. The tasks also require working well with the different departments at S&C Electric, such as quality assurance, Software Engineering, Mechanical Engineer and purchasing to achieve a design that was cost effective, delivered in timely manner, and met many customer requirements.
• Support qualification testing (ESD, endurance, HALT etc )
• Response for all EMI, FCC compliance.
- Senior Analog Design Engineer at S&C Electric Company
- Senior Analog Design Engineer at Curtiss Wright Corporation
- Senior Analog Design Engineer at Orbital Science Corporation/ Space Systems Group
- Analog Design Engineer at United Technology Corporation
3 years, 6 months at this Job
- Bachelor of Electrical Engineering - Electrical Engineering
4 x 25 GB/s SiGe Trans-Impedance Amplifier (TIA) ARRAY Design (2016.6-Present） Designed new blocks for TIA array Designed the chip system Worked with digital design engineer in 4X25Gb/s TIA Array project Worked with layout engineer to optimize chip layout Became Consultant after moving to U.S. 25Gb/s SiGe TIA Design (2015.6-2016.5) Designed most blocks in TIA chip from scratch Designed the chip system Adopted bandwidth enhancement to improve performance. Worked with layout engineer to optimize chip layout, writing data sheet and package guide Worked with package engineers to package chips, bonding photo detector (PD) with TIA Worked with test engineers to test chips, measure bandwidth, sensitivity, gain, etc Analyzed measure data and make the design perfection for next tape out 10Gb/s CMOS TIA and 4 x 10 GB/s CMOS TIA ARRAY (2010.3-2015.5) Designed most blocks in TIA chip from scratch Designed the chip system Adopted bandwidth enhancement to improve performance. Worked with digital design engineer in 4X10Gb/s TIA Array project Worked with layout engineer to optimize chip layout, writing data sheet and package guide Worked with package engineers to package chips, bonding photo detector (PD) with TIA in TO-CAN Worked with system engineer to design evaluation board Worked with test engineers to test chips, measurement items including bandwidth, sensitivity, gain, high temperature performance, low temperature performance. Analyzed measure data and made the design perfection for full mask tape out 10Gb/s CMOS TIA had already used by customer, 4 x 10Gb/s TIA ARRAY was sampling Supported customers 2.5Gb/s CMOS TIA Design (2008.1-2010.2) Designed TIA Core, AMP, AGC, DC_offset, Output_buffer, etc. Whole chip simulation Worked with layout engineer to optimize chip layout, writing data sheet and package guide Worked with package engineers to package chips, bonding photo detector (PD) with TIA in TO-CAN Worked with system engineer to design evaluation board Worked with test engineers to test chips, measurement items including bandwidth, sensitivity, gain, high temperature performance, low temperature performance Analyzed measure data and made the design perfection for full mask tape out Already delivered as product to customer Supported customers
- Analog Design Engineer at SiFotonics Technologies
8 years, 11 months at this Job
- PHD of Circuit and System - Circuit and System
- Master degree of Physicals - Physicals
- Bachelor degree of Physicals - Physicals
A member of the data converter design team focused on automotive products: · Designed analog IP blocks: 40nm and 90nm: temperature sensors, bias-generation 28nm: analog building blocks for a VCO-based continuous time 12-bit sigma-delta ADC 55nm: all-preamp based 4-bit quantizer for a continuous time sigma-delta ADC · Provided design and simulation support for analog IP blocks: 55nm: 12-bit DAC, sigma-delta ADC building blocks, sample & hold, regulators 40nm: wide-swing op-amp for a 12-bit DAC output buffering Hip6mw2: 4-bit quantizer for a continuous time sigma-delta ADC 16nm: 14-bit incremental ADC analog building blocks · Laid-out custom analog blocks in 40nm and 28nm technology nodes · Drove cross-team collaborations to execute and support tape-out of analog IP test vehicles in 40nm: Top-level & IP integration and signoff checks, and MEBES review · Test and validation experience for high performance analog IPs. Drove cross-team collaborations to test and characterize: Sigma-delta ADCs 12-bit DAC Temperature sensors · Key contributor across organizational boundaries to facilitate changes and improvements to PDKs, models, and simulations tools · Developed the model and system architecture (using MATLAB, Simulink, and VerilogA) for a 14-bit incremental ADC/Calibration to be used within a high accuracy temperature sensor IP in 16nm. · Developed the model and system architecture (using MATLAB and VerilogA) for a mismatch and offset insensitive single-ended cyclic ADC. One patent granted: 10,069,507 · Developed the model and system architecture (using VerilogA) for a 2nd order discrete-time sigma-delta ADC (with ADC run time diagnostics). One patent granted: 9,509,332 · Developed the model (including all static and dynamic non-idealities) for a 10-bit DAC for WIFI applications · Instrumental in implementation of technical documentations · Contributed key technical expertise to design reviews and literature studies
- Analog Design Engineer at NXP Semiconductors Austin
6 years, 8 months at this Job
- non-degree - Electrical Engineering
- Master of Science - Electrical and Computer Engineering
- Bachelor of Science - Computer (Hardware) Engineering
8-bit microcontroller business unit
• Currently working on the design of an on-chip, external capacitorless low-dropout voltage regulator for PIC and AVR load current requirements.
• Worked on the sub-blocks of a 12-bit SAR ADC.
• MATLAB macros to model CDAC, RDAC, signal paths and effects of non-idealities on ADC performance.
• Concept and design of an internal single ended buffer with improved slew rate, RDAC, and timing control block
• Worked on the concept and design of a multi-mode, low current, dual-voltage, self-regulated charge pump system for LCD applications and filed a patent.
• Designed a low power, low area bipolar bandgap reference with the auxiliary circuits to support PIC requirements.
• Initiated the design of an optimized on-chip temperature sensor with improved range, sensitivity, linearity, and voltage spread over process.
• Worked on a proof of concept and layout of a low-power current mode bandgap reference with improved decoding scheme for the voltage calibration block for reduced area.
• Worked on multiple current reference blocks to support PIC analog peripherals.
• Worked on an ultra-low power regulator for microcontroller sleep mode.
• Designed a low area, multi-mode, 5MHz programmable gain amplifier with 1% gain error spec.
• Bench validation and characterization of analog circuits on silicon
- Sr. Analog Design Engineer at Microchip Technology Inc
- Analog Architect at Microchip Technology Inc
5 years, 5 months at this Job
- Master of Science in Engineering - Electrical Engineering
Cobham, Hauppauge, NY
• Purchased current license for OrCad-Pspice A/D: Analysis of satellite antenna control system, operational control and power inverters. Aries Corporation, Littleton CO
• OrCad-Pspice A/D: verification simulation of satellite control system hardware MIL-PRF documents. Involved component model download from manufacturers and model parameter modification for worst case performance degradation due to component radiation and temperature effects. L-3 COM Infrared, Dallas TX
• MatLab: wrote programs to analyze long wave infrared image array noise characteristics.
• 0.18u CMOS ASIC verification: Using transistor level schematics and device layout files, set up test conditions and recorded image data to improve image array signal processing performance.
• High Vacuum Equipment, analyzed the image array performance as a function of internal vacuum level. Cypris Data Systems, Denver CO
• Control Systems: PID controlled in the MS-Windows device driver Cpp code.
• Discrete analog/digital: High speed multiple input data acquisition system was designed utilizing Xilinx FPGAs for signal processing and device control. Used ModelSim program for simulation and Xilinx tools for logic synthesis.
• Reel servo oscillation prevented shipment of reel to reel data recorders. The design solution was a control modification which compensated for the previously incompatibility of the existing reel motor controller and the new replacement motors.
• Thick film hybrid failure combined with no replacement inventory prevented repair of customer machines. With SMD technology, the Thick film module was re-designed at a much lower replacement cost. Cypris Data Systems, Los Angles CA
• Assisted in the re-design of a high speed data acquisition system.
• PWB design, component decoupling, supply circuitry (& hot) switching, signal transmission lines, low level/sensitive analog, HyperLynx was used to analyze digital signal propagation in a computer controlled data acquisition system. MaxCore, Colorado Springs CO
• Designed and manufactured a production tester for DLT (Digital Linear Tape) drive. Orbit Semiconductor, Sunnyvale CA (Merged with Flextronics Semiconductor)
• Cadence tools on Sun Microsystems: 0.5 micron CMOS mixed mode ASIC design: Designed analog front end for a water usage meter. The design was comprised of a front end amplifier (5MHz), 0 + 90 degree synchronous demodulator, filter and amplifier. Contributed to the ADC, significant Verilog for digital signal processing & control, analog layout and I/O placement.
• Cadence software was used for Spice and Verilog mixed mode simulation. Designed and fabricated a test assembly for this sub component testing. This was a standard cell design. Other: Metrum, Alient, Honeywell, Pinnacle Micro, Lockheed-Martin (previously Martin Marietta)
• Xilinx: system timing and digital data recovery system for helical scan recorder.
• Patented a calibration system for longitudinal data recording system
• Magneto optical laser drivers and data recovery. ; technical reading, have taken various MEAD Integrated Circuit Design Education courses in Analog ASIC design, Cadence Software, and other training courses.
• 8+ years of UNIX-OS experience, Fedora Red Hat, Ubuntu Mint Linux.
• Lived and worked as an electronic design engineer in Darmstadt Germany. Revision Date: November 4, 2018
- Analog Design Engineer at Cobham
- Design Verification Engineer at Cobham
at this Job
• Design of boost converter ◦ Mimimum input 0.8V ◦ Driver design ◦ Control logics design ◦ Chip comes back functional. Vin is 0.8V-3.3V. Vout is 2.5V-3.3V.
- Analog Design Engineer at zglue Inc
- Senior Analog Design Engineer in Power Management Group at Marvell Technology Group Ltd
- Driver design at Marvell Technology Group Ltd
- Research Assistant at Electrical Engineering Department, University of Tennessee
1 year, 7 months at this Job
- Ph.D. - Electrical Engineering
Design of 2 projects. Odyssey Service Interface, a Freescale processor based system to allow cloud access from service center to selected Diebold ATM's for remote diagnostics. Second, design of a power and USB distribution system to provide controlled power and communications to all modules used within the ATM. Used to reduce service calls to any ATM.
- Digital & Analog Design Engineer at Diebold Inc
- Digital & Analog Design Engineer at Pole/Zero Corporation
- A Lead team member in the design of a multiple at Lucent Technologies Series II
- Digital & Analog Design Engineer at Andrew Corporation
2 years, 1 month at this Job
Designed, developed and tested embedded memory design. Various memory types: SRAM, DPSRAM, ROM, OTP, EEPROM, Register
- SENIOR ANALOG DESIGN ENGINEER at Texas Instruments Inc
- PRINCIPLE CIRCUIT DESIGN ENGINEER at File
- CUSTOM MEMORY CIRCUITS DESIGN ENGINEER at LSI Logic Corp
- SOFTWARE DESIGN ENGINEER at LSI Logic Corp
7 years, 9 months at this Job
Designed CMOS analog cells and mixed signal chips for the automotive and industrial ASIC markets.
• Technical Lead o Contributed to design wins by verifying technical feasibility, estimating costs, and man power allocation for incoming projects. o Drafted specifications to meet customer requirements. Break down chip level specifications into block and cell level specifications for design team. o Lead teams of 4 to 6 engineers to design cells, blocks, and chips. o Build chip level schematics and simulations using Cadence design tools and Spectre simulator. o Generated chip level floorplan, define timing critical signal paths for chip level layout and place and route. o Evaluate silicon at chip level and cell level vs. product specifications. o Supported Product Engineering and Failure Analysis for silicon debug and finding root cause for customer returns.
• Analog Design Engineer o Worked with Technical lead to define cell specifications. o Design cells to specification. o Mentor junior staff members. o Generate floorplan and define critical paths for layout team.
• Design Failure Modes and Effects Analysis(DFMEA) Expert o Served as local expert for all DFMEA's produced in local design group. o Provided feedback to DFMEA team on updates to DFMEA flow. o Trained all local automotive personnel on DFMEA procedures.
• Example Work
- Senior Mixed Signal Design Engineer at ON Semiconductor
- Mixed Signal Test Engineer at Micron
- Mixed Signal Test Engineer at ON Semiconductor
17 years, 9 months at this Job
- Bachelors in Engineering - Engineering
Analog IC IP design in 7nm LP Technology: current reference circuits, voltage reference, a negative capacitance circuit for 60Gbps and/or 112Gbps PCIe Serdes and performed EMIR, self-heating, reliability analysis, and LVS and DRC layout extraction.
● Designed ultra-low power bandgrap (<1uA), voltage and current reference circuits for a medical device in 55nm technology.
● Designing fully-differential baseband transimpedance anti-aliasing filter and a logic frequency divider from 2GHz to 500MHz with 25% duty cycle in 120nm CMOS RF technology.
● Analog IC IP, such as LDO (voltage regulators), and bandgaps for DDR4 PHY integrated circuits with 14nm FinFet Technology, and performed EMIR, self-heating, and LVS and DRC layout extraction.
- Analog IC Design Engineer at ASIC North
- Analog Design Engineer at Toko America Inc
- Design Engineer at Ridgetop Group Inc
- IC Analog Design Engineer, Power Management Team at Motorola Inc
4 years at this Job
- MS - Electrical Engineering
- BS - Electrical and Computer Engineering