• Have worked on multiple SOC partitions, test chips and mixed signal designs in multiple roles. From partition owner, to top level chip owner to Formality signoff and various tool evaluations.
• Top level owner on multiple chips. Responsible for area estimation, block floorplan, pin assignment, channel routing, clock distribution, and floorplan pushdown to block owners.
• Experience leading design meetings and setting schedules, interfacing with PV/IR/STA teams.
• Member of the SOC Design Team, responsible for block level physical design implementation from netlist to GDS. Responsible for several blocks on multiple projects. Working on the latest process nodes.
• P&R tool evaluation of competing EDA vendor tools. Evaluated QoR and performance.
- ASIC Design Engineer IV at Apple
- Senior Design Engineer at Microprocessor Design Group
- Design Engineer at Microprocessor Design Group
- Design Engineer at Microprocessor Design Group
7 years at this Job
- M.S. - Electrical Engineering
- B.S. - Computer Systems Engineering
• Reviewed the IEEE Standard 802.3ae for 10Gb/s Ethernet.
• Developed the design specifications and micro-architecture for the Ethernet Media access controller.
• Designing digital logic modules for Ethernet MAC using Verilog RTL.
• Debugging with behavioral simulation and logic synthesis using Xilinx Vivado with directed testbench.
• Collaborating with the analog team to develop and design the Physical layer.
• Testing the design on FPGA - Xilinx Virtex UltraScale using VIO and ILA.
• Integrating and optimizing the MAC and PHY layer block
• Leading a team of 4 engineers to develop, design and verify the ASIC/FPGA/SoC Design to work through the MAC, PHY and the interfaces.
- ASIC DESIGN ENGINEER at Scalable Systems Research Labs
1 year, 5 months at this Job
- Master of Science - Electrical Engineering
- Bachelor's - Electronics and Telecommunication
Run DCG Synthesis /STA on chip SOC level for Qualcomm Snapdragon MSM. RTL design, Verilog, System Verilog, Spyglass. Run VCS for RTL/GL simulations. Primiteme STA, LEC for FV. Run CLP for UPF checks. DCG Synopsys, UPF synthesis, create power intent. Convert design flow from 7nm process to 5nm process
- ASIC implementation /ASIC design engineer at Qualcomm
- ASIC design engineer at Synapse DA
- ASIC design staff engineer at Marvell Semiconductor
- Design Engineer at Motorola Semiconductor
11 months at this Job
- M Sc in EE - EE
• Reviewed the Physical layer in the IEEE 802.3ae for 10Gb Ethernet.
• Developed the design specifications and microarchitecture for 10GBASE-T PHY.
• Designed the Descrambler, CRC, 64B/65B framer using Verilog RTL.
• Performed simulation and synthesis with flat testbench using Xilinx Vivado.
• Developing and designing the 10GBASE-X for the PHY.
- Junior ASIC Design Engineer at scalable system research labs
6 months at this Job
- Master of Science - Electrical & Electronics Engineering
- Bachelor of Technology - Instrumentation and Control
- ASIC Design Engineer Intern at Uniquify Inc
- Summer Research Intern at ReGen Powertech
3 months at this Job
- M.S Electrical - Electrical and Computer Engineering
- B.E - Electronics and Communication Engineering
Perform the following tasks such as writing Design and Development, RTL coding/fixing, Simulation, Sythesis , Lint checking, Clock Domain Crossing(CDC) Analysis, Scan insertion for DFT, Formal Verification, Floorplanning, Power Planning, Place & Route, LVS/DRC/Antenna clean , final sign-off using for Static Timing Analysis(STA), Power Analysis, Integration for Cluster level & Toplevel and also resolving SI issues for the following companies listed below.
• ASIC Design Contractor Engineer for Analog Device Corporation, Santa Clara, CA, HDMI 2.1 project with operating frequency High speed(650Mz for both transmitter and receiver ) and Super Low power consumer electronics device. The design size is more than 15 million gate design targeted for 10nm technology using TSMC library which consists of nine layers of metal. Responsible for four critical blocks including Top level with large no. of hard macros in one of the design, RTL fixing, Synthesis(using Cadence Genus), Constraint writing and fixing, Formal Verification(Cadence Conformal) for Low Power, CPF ,UPF, DFT, restricted and efficient multi-voltage(4-voltage domain) floor-plan methods to reduce the Congestion, to obtain the best Area, Timing and Power. Used Innovus for initial Place and Route, Clock Trees Synthesis, with latest clock tree Synthesis technique to reduce the Skew and Timing failure, LVS/DRC, Antenna Clean, Cadence Tempus for Timing Closure, Crosstalk Analysis, Voltus for IR-Drop Analysis. Mentor Graphic Caliber for LVS/DRC/Antenna clean Sign Off. Responsible for block level full chip integration, Timing and design closure. Managed team consists of four persons. Flow automation using Tcl, and Perl. Aug'2017 - Till date
- ASIC Design Contractor Engineer at DFT, Formal Verification
- ASIC Design Contractor Engineer at Intel Corporation
- ASIC Design Engineer at Aeroflex Design
- ASIC Design Service Engineer at Cadence Design Systems
1 year, 5 months at this Job
- PhD - Computer Science and Engineering
- MS - Electronics and Telecommunication Engineering
Touch Sensor ASIC Team Leader and Architect: trans-capacitor touch sensor, self-capacitor touch
sensor, finger print touch sensor. Tape out four generation chip sets from concept to mass
• Touch Sensor ASIC Logic Design: power/ reset/ clock/ timer/ port controller, I2c/ spi/ interrupt/ adc/ scaler/ tx_scan controller, phase/ frequency/ baseline filter, touch/ gesture detector, loss/ lossless compress coder.
• Touch Sensor Multi-finger Tracking and Processing Algorithm Design: adaptive finger detecting and tracking, power interference and coupling noise detecting, data association of multi-finger tracking, non-cross nearest neighbor matching, tracking Kalman filtering, gamma and edge correcting, denoise and deshake processing, figure gesture detecting and recognizing.
• Develop and implement gesture detection and recognition algorithm with Matlab and implement with hardware engine (only 0.3MA power consumption vs 4MA competing products).
• Design and implement universal serialize-deserialize interface between digital controller and analog circuit, verification with FPGA for first time tape-out success.
• Define product requirement, manage design flow and schedule, coordinate manufacture, test and package partners, train FAE team, coordinate and solve customer important technical issues.
• Manage the design process from concept to silicon with extensive and comprehensive coordination and cooperation with ASIC design, RTL verification, FPGA emulation, software and firmware development, testing system and platform.
- ASIC Design Manager at Truecore Microelectronics Inc
- ASIC Design Manager at Cadrado Inc
- ASIC Design Engineer at ESS Technology Inc
- Senior Hardware/FPGA Engineer at UT-StarCom
5 years, 9 months at this Job
- MSEE - Electrical Engineering
- BSEE - Electrical Engineering
• Working on Micro-architecture for HDMI 2.1 transceiver 28nm Chip
• Working on Micro-architecture for SERDES PLL design 10nm Chip.
• Chip and IP level integration, using latest ASIC tools from DC/DC-T, and FV.
• Low Power UPF design flow generation using VCLP & SpyGlass/LP.
• Regression test benches consistency and resolving Low Power design UPF checking.
- Sr. IC Design Engineer/Architect at Intel
- Sr. IC Design Engineer IV at Qualcomm
- Sr. Staff IC Design Engineer at AMBA Traffic Generators
- Sr. Staff IC Design Engineer IV at Qualcomm
7 months at this Job
- Ph.D - 1st part
- BSEE - Electronics and Telecommunication
RTL design of Lattice CrossLink FPGA using Lattice Diamond and Synopsys Synplify, to provide a bridge from 2-lane, 324 MHz MIPI-DSI stream to Kopin nHD2 micro-display driver ASIC (A254 & A255 versions). Simulation environment developed/run using Aldec Active-HDL. H/W debug on 4 prototype board configurations. Interface to the ASIC is via 108 MHz DDR link.
- Senior FPGA Design Engineer (working remotely from San Jose office) at Kopin Corp
- Senior FPGA Design Engineer at KLA-Tencor
- Senior ASIC Design Engineer at Semtech Inc
- Senior ASIC Design Engineer at Avago Technologies (now Broadcom)
10 months at this Job
- Bachelor's - Electrical Engineering
- Master's - Electrical Engineering
TRONICS MEMS, Inc. - Richardson, TX
• In collaboration with the President of U.S. Operations, managed successful sales campaigns from qualification through closing for global MEMS medical devices, wearable electronics, and other applications. This led to key customer acquisitions and project wins, increased NRE and production purchases in excess of several million dollars.
• Aided in resolving customer challenges during pre and post sales efforts by conducting site visits via international travel to Europe and domestically, and by providing additional support by phone, and email communications. This resulted in creation and restoration of customer trust and confidence, which led to continued engagement for future business opportunities.
• Provided forecasts, and revenue updates to France and U.S. staff, on pipeline and future business opportunities. This improved monitoring of customer activity and invoices to make decisions regarding the financial health and direction of the Company.
• Collaborated with Business Development and Corporate Sales teams to take new leads through qualification, while contributing to managing the quotation process through aiding in generation of RFQs and RFPs. This resulted in increased purchase orders and additional revenue streams from customers.
• Contributed to business contract negotiations with Customer Management, Tronics Corporate Management team, and Legal Counsel, during redlining of Master Agreements. This resulted in winning several key revenue generating customers in less than six months.
• As a key contributor in the Customer Relations area, participated in the auditing process, which led to Tronics U.S.'s most recent ISO9001 certification.
• Created and disseminated information for Quarterly Review for ISO9001 compliance, which provided a framework to ensure continued compliance to commitments for the industry recognized quality management system. Expected to allow for acquisition of new customers by creating confidence through conformance to standards, regulations, business practices and requirements for Tronics products and services.
• Responded to customer requirements and inquiries, facilitated discussions integrating four primary management teams, Engineering, Quality, Customer Programs, and Corporate. This led to qualifying accounts and business wins for U.S. and France engagement activities.
• Provided presentations to global Corporate Executive Management biweekly, weekly for local Staff Management, and monthly Corporate Internal Communications Meeting for US employees. Resulted in increased synergy between US and Europe operations as well as increased collaboration between project efforts.
• Initiated discovery for incoming requests from interested Asian prospects. Information gathering, knowledge sharing, and transfer to a distributor, led to ongoing efforts to broaden presence in Asia, through collaboration with France and China. CADENCE DESIGN SYSTEMS, Inc. - Addison/Plano TX LEAD PRE-SALES APPLICATIONS ENGINEER (TECHNICAL SALES CONSULTANT)
• As a product specialist for Incisive Verification suite, managed and conducted successful presales technical campaigns in uncovering and supporting opportunities in Texas, Arizona, and Colorado to increase product sales. Resulted in significant reduction of the sales cycle, and in seeding other Cadence products and platforms into customer accounts.
• Collaborated with multiple sales account teams, C Level management, Marketing, R&D (foreign and domestic), and peers, for enterprise and geography accounts to strategize engagement and execution plans for preexisting and new customers. Resulted in securing multimillions of dollars in revenue for Cadence, and in customer satisfaction.
• Created and provided customized product demos for trade shows, seminars, and prospects. Sparked increased interest, offering a strong value proposition to help customers reduce their verification time, in order to shorten their design cycle and increase their time to market.
• Engaged in and executed competitive product benchmarking through evaluations, eliminating competition from customer accounts through providing performance improvements, resulting in 200% performance improvement and reduction of the customer verification time by 50%.
• Provided methodology and flow assessment, migration path recommendations, usability and quality enhancement for RTP, excellent quality support through relational and technical skills, problem management from inception, to escalation, to timely resolution. Resulted in receiving Customer special recognitions and allowed for transition from competing tools to Cadence software.
• Provided rollout training to the user community, lunch and learns, and created Application Notes to aid in customer use model. Resulted in accolades from customers and smooth transition from competing tools.
• Positive written feedback received from VP of TFO and Corporate for internal evaluation of acquired technology. Extracted, evaluated, composed and provided detailed document used as the primary decision-making criteria for tool selection for release to market. VLSI/PHILIPS SEMICONDUCTORS - Richardson, TX ASIC DESIGN ENGINEER
• Utilization of standard cell libraries (.35u, .25u, .2u) in creation and debug of ASIC flow. Led to physical design and sales of telecommunications applications in automotive, broadband, and other markets.
• Efficient multitasking on concurrent designs resulted in high quality production parts, using bleeding-edge technology that both met and exceeded expectations in each job assignment.
• Worked with external customers and design team in utilizing problem-solving skills for project challenges, resulting in high yield production parts for telecom and other applications.
• Utilized effective communication skills through flow implementations. Trailblazer for formal design verification flow on what management considered the most complex design in the technology center community. Resulted in reduced time to market for ASIC.
• Created application notes, later incorporated as a standard in the verification methodology for future designs. Executed problem-solving skills through Formal Verification, Place and Route, Physical Verification, Extraction, Memory Generation, Chip Level Power Estimation, used Package Constraints Manager in creation and submission of bonding diagrams to packaging for approval. First Pass Silicon success allowed for customer retention, and future design wins. TEXAS INSTRUMENTS - Richardson/Dallas, TX DIGITAL IC DESIGN ENGINEER/APPLICATIONS ENGINEER As a Digital IC Designer:
• Became a trailblazer in the Telecom Audio Design Group to design, develop, and characterize digital designs from kickoff to release to production with the Mixed Signal Telecom/Wireless Business Unit. Digital interface design for external customer requirements such as for the NOKIA's GSM/JDC standards for mobile phones and for internal catalog parts.
• Coded VHDL behavior level software for two concurrent designs and RTL for synthesis for PCM interface design, which met time to market requirements.
• RTL/Gate Level Verification of interfaces resulted in becoming a liaison for Cadence and team.
• Made design review presentations to key NOKIA personnel from Finland, which led to a successful engagement plan and purchasing of TI chips by NOKIA. Overall results contributed to first pass silicon on each design. By 2000, millions of units were sold and were in production. Revenue from designs helped TI become the global leader in Mixed Signal Products. Those chips used in cellular telephony boosted profits and company morale through bonuses, higher stock prices and promoted continued partnerships for both TI and NOKIA. As an Applications Engineer:
• Provided quality support for ASIC back-plane customers (internal/external). Trained and provided tool guidance for customers in California and Colorado. Acted as a liaison between corporate ASIC and the customers for TIDDS related questions, handling standard cell and gate array strategic/tactical cell issues from kickoff to production, and creation of tactical embedded arrays for base array designs. Led to acquisition of key customer. ALCATEL NETWORK SYSTEMS, Richardson TX (Summer Intern) SONET Engineer / Software Support Summer Hire:
• Performed Jitter Analysis of 1603 and 1648 SONET Multiplexer testing. Monitored TAR tracking through use of Interleaf software. Provided assistance to offsite users of the SONETs, and created test bed layout in R&D. Those actions paved the way for lengthening the product cycle of the 1603 and 1648 SONETs. ROCKWELL INTERNATIONAL, Richardson, TX (Summer Intern) General Engineering Summer Hire:
• Compiled inventory status lists for military components and analyzed military specs for parts dimensioning in PCB library. Updated parts library by recalculating dimensions and sketching new dimensions with proper specs. Archived old drawings and relevant data in secure room with security clearance. Composed document change notifications, compared netlists with hand drawn schematics. These actions resulted in organization of military archives, and ease of access, thereby shortening the design cycle, as well as time to market for military parts. TOOLS AND PLATFORMS Windows Platforms VLSI/Philips/TI ASIC Tools Design Compiler Solaris NC-Verilog LSim HP-UX NC-VHDL TimeMill LINUX, NC-Sim Formality Macintosh Verilog-XL Primetime UNIX Leapfrog Modelsim Smartsheet Incisive Coverage Technology Apollo Sharepoint Static Check Hercules DRC/LVS Office 360 Assertion Based Verification Calibre DRC/LVS VHDL Advanced Model Packager STAR RC Verilog Verifault FORTRAN HAL
- Sales Engineer at Tronics MEMS, Inc.
at this Job