Monterey Road, CA
• Designing MIPS64 components - ALU and control unit According to ISA.
• Write, Execute and Debug Verilog and SystemVerilog test benches using Xilinx Vivado tool.
• Edit and run existing Perl scripts to automate processes in the Verification environment.
- ASIC Engineer - Intern at Scalable Systems Research Labs
- Software Engineer at KPIT Technologies
4 years, 3 months at this Job
- Masters of Science - Electrical Engineering
- Bachelor - Electronics and Communication Engineering
• Worked on the processor for automotive-self driving vehicles which is a CPU+GPU unit
• Worked on the validation of the compiler and optimizer modules of the CPU unit
• Worked as a part of the post FPGA and post silicon verification team
- ASIC ENGINEER at Nvidia
- HARDWARE VERIFICATION ENGINEER at
- INTERN at Nvidia
- SUMMER RESEARCH INTERN, POWER ELECTRONICS TEAM at Defense Research and Development Organization
1 year, 6 months at this Job
- M.S - ELECTRICAL AND COMPUTER ENGINEERING
- B.E.(HONS - ELECTRONICS & INSTRUMENTATION ENGINEERING
* Lead (hands-on) the integration of security IPs in a set-top box ASIC for a Conditional Access System vendor certification * Architected and implemented a linked-list based N-port Ethernet Switch * Proposed and co-implemented Ethernet subsystem related hardware enhancements * Architected and lead the implementation of DOCSIS-3.0 MAC hardware
- Principal ASIC Engineer at Sigma Designs
- Sr.Staff Engineer at NXP (Philips) Semiconductors
- Sr.Design Engineer at HCL-HP Ltd.
- Design Engineer at Compsoft Ltd
1 year, 6 months at this Job
- Masters - Micro-electronics
- B.E - Electronics & Communication
Senior ASIC Engineer: Engineer the many ASIC EDA processes required to bring an ASIC component into production fabrication, such as logic synthesis, DFT scan insertion and ATPG, logic equivalency checking, clock domain crossing and power analysis.
- Contract Consultant Engineer at Advanced Micro Devices (AMD)
- Senior Staff Engineer at Seagate Technology
- Principle Test Engineer in the ASIC at Maxtor/Quantum Corporation
3 years at this Job
Hands-on ASIC manager and SoC architecture leading ASIC and FPGA development in the area of DSL noise cancellation.
• Designed and validated product prototype with multiple Virtex6 FPGAs for successful field trial.
• Delivered first-pass working DSL noise cancellation ASIC (65nm) for customer deployment.
• Effectively worked with system and firmware teams to architect SoC and major DSP cores.
• Led chip design with custom DSP logic, AXI based NoC, multi-CPUs and peripherals.
• Championed external IP selection and integration: NoC, ADC, DAC, PLL, DDR and LVDS.
• Hands on SoC integration with I2C, SPI, MMC, Ethernet MAC, DMA and DDR PHY.
• Analyzed complex signal processing algorithms and derived area efficient fixed point implementation.
• Enhanced verification with system Verilog assertions and constrained random testing.
• Drove physical design execution and product qualification with external design service partner.
• Experienced in chip lab bring up, post-silicon debugging and product qualification and characterization.
• Evaluated design tools, negotiated with CAD vendors and managed tool installation and licensing.
- Sr. Manager, ASIC Engineering at ASSIA Inc
- Sr. Principal Engineer / Chip Lead at Broadcom / AMD / ATI
- Member of Technical Staff at Lucent Technologies
- Product Engineer at Advanced Micro Devices
8 years at this Job
Work on multi-media IPTV chips ⚫ Work on clock/reset generation (dynamic/reconfigurable glitch-free clock switch, clock divider, reset re-synchronization logic with clock delay and gating, chip level clock generation logic, chip level reset generation logic): RTL Verilog coding & simulation ⚫ Work on SoC chip level integration and handoff: PLL, POR, clock/reset, interconnection (bus/crossbar/NoC), pad pinmuxing, system configuration, and DFT connection ⚫ Work on image processing algorithm implementation (color space conversion, gamma correction, color component interpolation): RTL & simulation ⚫ Work on low power design: architecture and implementation (multi- power islands, DVFS, power up/down control logic) ⚫ Work on synthesis and timing closure: SDC, setup/hold violation analysis & fix 1 ⚫ Work on SoC chip architecture: IP evaluation, block partition, interfacing, and ESL evaluation
- Chief Engineer at ZTE TX
- Principal Scientist at Broadcom Corporation
- Senior SoC Engineer at MediaWorks Integrated Systems, Inc
- System/ASIC Engineer at Technology, Inc
6 years at this Job
- Ph. D. in Electrical Engineering - Electrical Engineering
- M. S. in Electrical Engineering - Automation
- B. S. in Electrical Engineering - Automation
Responsible for implementing scan into existing subsystem design, which entailed removing previous scan. Perform many different tasks including bug fixes on existing design, Spyglass CDC conformity, Spyglass DFT conformity, logic change and fixes, timing analysis, formal equivalence review. Received recognition award for helping to implement new scan design and protocol, along with test group. Implemented MBIST into existing memory designs, replacing previous LV-mbist. Developed validation collateral for SOC-level testing and verification. Responsible for IP-integration into men subsystem, consuming over 15 different IPs into the subsystem.
- Senior Engineer at Intel
- ASIC ENGINEER at AVAGO TECHNOLOGIES/BROADCOM
- SENIOR ASIC DESIGNER at FREESCALE SEMICONDUCTOR
- ASIC ENGINEER at FUJITSU
1 year, 11 months at this Job
Algorithmic Lookup/Search Engines. Combination of TCAM and algorithmic SRAM lookups. Cloud infrastructure chips.
• O3: A0-Block verification: RPT/PCT verification. Setup Power gating flow for design and verification. B0: Verification Lead. Chip level Sims and overall chip level verification
• OP Verification Lead. ◦ Setup initial flows and manage different block level verification. Divide tasks for various blocks. ◦ Full chip verification including application cases and performance tests. ◦ Emulation Lead. Setup. First time emulation in our group. ◦ Wrote scripts to build emulation image in 3-4 hours. ◦ Bringup chip in lab and see it through production.
• OP2 Emulation: Setup the flow for the new chip, generate images and manage tests to be run on the emulator.
• Cloud infrastructure chips. Block level verification of different blocks.
- Sr Principal Engineer @ Netlogic at Broadcom Inc
- Sr Member at Technical Staff @ AMD Inc
- Design USB ISO Endpoint controller for video at Contracting @ Zoran(5), Foveon(5), Tessera Inc(3)
- Sr ASIC Engineer at Nvidia Inc
7 years, 2 months at this Job
- Masters of Science in Computer Engineering - Computer Engineering
Design and reverse engineering of embedded systems. Test fixture design and development.
• Performed side channel power and glitching attacks on several families of micro-controllers using NewAE Chip-Whisperer. Designed target specific PCBA's to interface with the Chip- Whisperer. Wrote Python code to control attacks, communicate with target micro-controllers, and monitor for success.
• Worked with outside chip reverse engineering houses for low level chip level analysis. Wrote RFQ's for chip de-processing, imagery, memory extraction, and chip level timing and glitch attacks.
• Reverse engineering of assembly code.
• In order to save in house R&D resources, developed relationship with outside fixture house to quickly develop a range of bed-of-nails test fixtures. Wrote hardware and electrical specifications for test fixtures. Fixtures were designed to be flexible and durable enough for high volume CM production and FCT testing. Fixtures were also used for in-house programming of final product.
• Configured Cyclone Universal and Prime 8 programmers for programming of multiple micro- controller families.
• Altium \ Eagle PCB design. Layout to minimize EMI, maintain signal integrity, and control capacitance of RF critical nets.
• Design, test, and qualification of ISM band PCB loop antennas. Adjusted antenna impedance to 50Ω. Designed matching network to modify transmitter output impedance to 50Ω, while minimizing harmonic content and giving maximum power transfer. Passed FCC Part 15 certification with over 3dB margin on multiple designs. Typically, achieved SWR's below 1.2. Used network analyzers, Smith chart simulation software, and software defined radios to verify design.
- Senior Analysis Engineer at Engineering Staff for Private Company
- Senior Development Engineer at Lexmark International Inc
- Senior ASIC Engineer at Lexmark International Inc
- Development Engineer at Lexmark International Inc
2 years, 8 months at this Job
- BS - Electrical Engineering
Fixed Wireless Access Radio
FPGA with an integrated radio unit uses a CPE in fixed wireless access system. Radio provides the baseband portion of the fixed wireless system, interfacing between IRU's mac layer processor and RF subsystem.
• Multi Point Back Haul System FPGA with an integrated radio unit uses a CPE in point to multi-point back haul system. Radio provides the baseband portion of the backhaul system, interfacing between IRU's mac layer processor and RF subsystem. ✓ Analyze and understand the New wireless Modulation, OTFS for wireless systems ✓ Create verification plans containing the test bench environment ✓ Developed the environment for fixed wireless access, Hub ✓ Created the test bench and test cases for fixed wireless access, CPE ✓ Tested the communication paths between Hub and CPE ✓ Collaborated with system and test teams to test, achieve product functionality. ✓ Developing test plans and coverage documentation from the given specifications. ✓ Create test bench, reference and coverage models, assertions and functional tests using Verilog and System Verilog. ✓ Coding test cases and performing regression based functional tests ✓ Automate the environments using the scripting languages like perl and shell. ✓ Performed chip bring up and debugging on FPGA
- Senior Systems Engineer/Verification at Cohere Technologies
- Senior ASIC Engineer (Consultant) -AMD at
- Senior ASIC Engineer at UVM
- ASIC Engineer at Soctronics
3 years, 8 months at this Job
- Master of Science - Electrical Engineering
- Master of Technology - VLSI Engineering
- Bachelor of Technology - Electronics/Communication