at this Job
- Master's - VLSI
Responsible for functional verification of critical data path blocks using System Verilog and UVM. Scheduler: Rate Shaping, Round Robin, Priority Scheduling and Performance testing. Congestion Management: Drop decisions, Flow control and other Resource Management. Other responsibilities include: Work with designers and architects to understand the features to be verified. Develop test environment including sequences, drivers, monitors and scoreboards. Develop previous generation testbenches to verify new feature set of the upcoming chips. Debug and logging of test failures from regressions. Review code and functional coverage. Sub-system, full chip verification, gate-level simulations, emulation and chip validation. Test plan, test objects and test scenarios documentation ownership and conducting exit reviews. Assisting lab engineers and software team in writing driver code for chip bring-up and debug.
- ASIC Engineer 3 at Juniper Networks
- Graduate Technical Intern at Rockwell Collins
- Graduate Assistant at NYU Polytechnic School
- Application Developer at IBM India Private Ltd
4 years, 6 months at this Job
- Master of Science - Electrical and Computer Engineering
- Bachelor of Engineering - Electronics and Communication Engineering
- Diploma in Electronics and Communication Engineering - Electronics and Communication Engineering
- ASIC verification engineer at microchip
3 years at this Job
- Studying MS
Working as a design verification engineer on 3 server SoC projects at Qualcomm, primary responsibilities are comprised of test planning and development (c-code/assembly/vera/systemVerilog UVM), testbench design and development, regression analysis and debug, bug tracking and resolution, coverage analysis and closure, as well as planning, development, and debug of post-silicon functional vectors.
Served as the verification lead for a team of 5 DV engineers to verify the first Qualcomm server application processor sub-system (48 64-bit ARMv8 cores and 12 L3 caches). Responsibilities in this role included test planning at both sub-system and SoC levels, the design and implementation of the sub-system testbench and environment using SystemVerilog UVM, development of portable test sequences (UVM and c-code) and drivers (c-code and assembly) for use at both sub-system and SoC, code and functional coverage analysis and closure, as well as resource planning and coordination for the team.
Additional responsibilities include maintenance and support for the server DV native build flow (c-code and assembly), debug support for processor sub-system issues, porting of existing testcases from various disparate environments into the server DV environment, interfacing with other teams, and mentoring of junior engineers.
• Successfully led Verification effort of first Qualcomm server application processor sub-system (48 cores and 12 L3 caches).
• Verified integration, interoperability, and use cases of ARM A53 based resource management and debug processor sub-systems in the 2nd generation server design.
• Ported make flow for all ARMv8 native (c & assembly) testcases and drivers from ARMTOOLS to LLVM & GNU ASM and linker, including required C and ASM updates to testcases and drivers.
• Worked with software team to implement tests for system use cases.
- Senior Staff Verification Engineer at Qualcomm, Datacenter Technologies
- Staff Verification Engineer at Qualcomm CDMA Technologies
- ASIC Design Engineer at multi-CPU
- ASIC Verification Engineer at Stratus Computer
9 years at this Job
- BSC - Electrical and Electronic Engineering
December 2005 - December 2015 (10 years) Canon Information Technologies Philippines, Inc., Eastwood City, Libis, Q.C., Philippines
- Design Verification Engineer at Canon Information Technologies Philippines, Inc
- Project Manger at Canon Information Technologies Philippines, Inc
10 years at this Job
- Bachelor's - Electronics and Communications Engineering
- Master's - Electrical and Electronics Engineering
- Bachelor's - Electrical and Electronics Engineering
- Bachelor's - Electrical and Electronics Engineering
I am an embedded systems engineer with CPU HW Architecture emphasis) and extensive experience with embedded Linux (including Busybox, uClinux ) and various RTOS implementations ( RTX/CMSIS, ThreadX, VxWorks, etc ). Experience in SSD / NVMe / PCIe technologies. Experience with ASIC and FPGA, verification and debug. Experienced in BSP development for multiple processor families ( ARM, PowerPC, MIPS, x86 ), and porting of bootloaders, operating systems, and other system-level firmware and drivers for onboard resources ( ethernet, storage, I2C, UART, RTC, A/D, D/A ) . Proficient with In-Circuit Emulators, JTAGS, Protocol Analyzers, etc. .Proficient in automating using Python, Perl, TCL/Expect, Lua, Ruby, PowerShell
Western Digital / Sandisk Longmont CO Aug 2017 - Present
SSD ASIC Verification Engineer
● Performed ASIC Pre-Silicon Verification tests for an SSD Controller Chipset supporting NVMe, SAS, and SATA hosts.
● Wrote tests for a complex back-end SoC containing multiple ARM and ARC processors which communicated directly with NAND flash..
● Wrote SECDED calculation memory algorithms and tests.
● Testing was performed across Behavioral ISS models, RTL System Verilog / UVM environments, and FPGA platforms.
● Wrote automated regression test suites to exercise SoC functionality.
● Wrote scripts to perform FW image "backdoor" load and ECC generation in RTL and FPGA environments.
● Wrote ARM C and Assembly code. Scripting was done using TCL/Expect Perl
● Identified problems, managed defect resolution and wrote bug fixes.
● Worked with distributed teams across the USA and Taiwan
- SSD ASIC Verification Engineer at SSD / NVMe / PCIe technologies
- Firmware Project Lead at Onicon Inc
- ARM FW Engineer at Rand McNally Corporation
- SOC FW Engineer at Futurewei/Huawei Corporation
1 year, 5 months at this Job
- BS - Computer Science
- Master's - Computer Architecture
Worked on the analysis of linear, nonlinear and multi-component linear FM signals. This project aimed at analysing a new algorithm for classification of these signals in low SNR (0-5dB) conditions. With insights from my mentor, I came up with a novel method using ‘Short Time Fourier Transform and Hough Transform’ and implemented it in Matlab. This was published in International Symposium on Signal Processing and Information Technology, 2015.
- RESEARCH INTERN at Defence Research and Development Organization
- ASIC Verification Engineer Intern at Nvidia Graphics
- SUMMER INTERN at HINDUSTAN AERONAUTICS LIMITED
- Product Development Intern at National Innovation Foundation
1 month at this Job
- M.S in Electrical Engineering - Electrical Engineering
- B.E - Electronics and Communication Engineering
Project management professional with responsibility for project planning, tracking and execution of various programs. Areas of expertise include Disaster Recovery, Audit and Client handling.
• Review and develop Business Interruption Plans and strategies to ensure the appropriate procedures are in place to recover business data/application and minimize recovery risks.
• Responsible for ensuring the Business Interruption plan effectively addresses the organization's requirements and within established time frames.
• Produce risk assessment and implement audit test plan for assigned audit areas to ensure compliance with company standard practices.
• Audit compliance was done in a very short time and during the process corrected many flaws in the system.
• Help the company to successfully complete the Ford Audit without any major comments from Ford and helped the company to get more projects from Ford.
• Created technical documents for the application handled and identified many bugs in the program.
• Identify and help to resolve the issues in programs related to application and data.
• Interface with both business and system personnel to ensure effective and timely delivery of project related deliverables.
• Define and directed project goals, objectives, critical success factors, milestones and risks.
• Provided overall management, monitoring, and control of Release activities (business, workflow, development, testing).
• Coordinate and conduct IT Tour for WIA Youth participants. WIA helps to educate and direct the youths to get job.
- Program Manager at Marketing Associates LLC
- Senior ASIC Verification Engineer at IBM
8 months at this Job
· Deliver data driven full stack solutions in response to customer business & technical requirements - involving architecting, designing, writing user stories and overseeing implementation to provide end to end solution/service for Big Data, cloud computing, website/app solutions, service consolidation and migration. · Cross team collaboration to drive the complete projects from voice of customer to delivery. · Create business cases, MRDs, PRDs, WBS, project charter, project report, product backlogs and risk reports. · Proactively manage changes in project scope, identify potential issues and risks, and devise contingency plan to ensure timely delivery.
- Business Development Manager at PS3G Inc
- SoC Design Engineer at Intel
- Verification Engineer at
- ASIC Verification Engineer at Nethra Imaging
9 months at this Job
- Certificate - Program and Project Management
- Master's - Electrical Engineering
- Bachelor of Engineering - Electronics and Power Engineering