Product: DRAM Tester ASIC
● Creatively involve random configuration into Python based verification flow, found 10+ bugs in design which were not able to be discovered by previous flow
- Senior ASIC Verification Engineer at Micron @Minneapolis, MN
- Senior II. Digital SoC Design Engineer at Starkey Hearing Technologies @Eden Prairie, MN
- Digital design team lead at Texas Instruments @Shanghai
- Staff Design Engineer at
1 year at this Job
- - design
As a verification engineer, worked in clients location Cypress Semiconductors developed" Reusable SV-OVM test-bench for programmable diviider clock"
- ASIC Verification Engineer at Wafer Space Semiconductors
1 year, 4 months at this Job
- Master's - VLSI
- ASIC verification engineer at microchip
3 years at this Job
- Studying MS
Carlsbad, CA (From L&T Technology Services till July 2017) March 2013 - Till date ✓ Developed and maintained verification methodology in UVM. ✓ Worked on the design of verification platforms for Modems, MAC processors and Ethernet. ✓ Was involved in all test plan reviews & verification strategy planning. ✓ Execute on test plans by writing block level and top level sequences & tests in UVM & C. ✓ Debug verification failures to root cause and working with RTL developers to fix and re-verify the designs. ✓ Release of the Full Chip design database with new versions of the IPs & top level design along with the verification environment to the DV team. ✓ Analyze and improve the functional coverage of the design. ✓ Supported the software team in diagnostic and testing activities. ✓ Responsible for GLS environment bring-up & GLS simulations for SOC & multiple IPs. ✓ Mentoring & leading junior verification engineers. ✓ Onsite Co-ordination, project estimation, planning, scheduling, resource management and prioritization across the teams in Chennai & Bangalore - India & San Diego - USA.
- Project Manager/Senior FPGA-ASIC Verification Engineer at Carriercomm Inc
- Verification Lead at Texas Instruments
- Senior Verification Engineer at Texas Instruments
- ASIC Verification Engineer at Texas Instruments
6 years at this Job
- M.S. - Micro Electronics
- B. E. - Electronics & Communications
Working as a design verification engineer on 3 server SoC projects at Qualcomm, primary responsibilities are comprised of test planning and development (c-code/assembly/vera/systemVerilog UVM), testbench design and development, regression analysis and debug, bug tracking and resolution, coverage analysis and closure, as well as planning, development, and debug of post-silicon functional vectors.
Served as the verification lead for a team of 5 DV engineers to verify the first Qualcomm server application processor sub-system (48 64-bit ARMv8 cores and 12 L3 caches). Responsibilities in this role included test planning at both sub-system and SoC levels, the design and implementation of the sub-system testbench and environment using SystemVerilog UVM, development of portable test sequences (UVM and c-code) and drivers (c-code and assembly) for use at both sub-system and SoC, code and functional coverage analysis and closure, as well as resource planning and coordination for the team.
Additional responsibilities include maintenance and support for the server DV native build flow (c-code and assembly), debug support for processor sub-system issues, porting of existing testcases from various disparate environments into the server DV environment, interfacing with other teams, and mentoring of junior engineers.
• Successfully led Verification effort of first Qualcomm server application processor sub-system (48 cores and 12 L3 caches).
• Verified integration, interoperability, and use cases of ARM A53 based resource management and debug processor sub-systems in the 2nd generation server design.
• Ported make flow for all ARMv8 native (c & assembly) testcases and drivers from ARMTOOLS to LLVM & GNU ASM and linker, including required C and ASM updates to testcases and drivers.
• Worked with software team to implement tests for system use cases.
- Senior Staff Verification Engineer at Qualcomm, Datacenter Technologies
- Staff Verification Engineer at Qualcomm CDMA Technologies
- ASIC Design Engineer at multi-CPU
- ASIC Verification Engineer at Stratus Computer
9 years, 2 months at this Job
- BSC - Electrical and Electronic Engineering
• Successively setup and debugged the Gate Level Simulation environment. VCS/Verdi/Perl
• Identified several major problems in RTL codes, RTL to Gate translations, methodology/enviromant setup scripts.
• Provided consultations to the design team that helped to trace and nailed down a very important bug.
- Contractor - CPU Verification Engineer / Gate Level Verification at ADVANCED MICRO DEVICE
- Principle Verification Engineer at ALTIERRE
- Contractor, ASIC Verification Engineer - ASIC Design Verification / UVM at QUALCOMM
- at San Jose State University
2 months at this Job
- MS - Electrical Engineering
- BS - Electrical and Computer Engineering
• Member of Agile DevOps team developing Perl / Python cross-platform test automation infrastructure, supporting Continuous Integration / Continuous Delivery of NetBackup, an enterprise-level backup solution for cloud, virtual, and physical environments.
• Supported major NetBackup initiatives which included security hardening, pure- IPv6, and Dynamic NAT firewall support.
• Implemented efficient resiliency for test result analysis Python microservice, through use of delayed retry message queue and dead-letter exchanges; involved use of Docker, Kubernetes, Artifactory, RabbitMQ, and PostgreSQL.
• Mentored interns working with us remotely from St. Cloud State Maverick Software Consulting.
• Completed Veritas Software Engineer Security training.
• Presented Hackathon demo on use of Directed Random Testing techniques to increase test coverage when time / resource budgets are constrained.
- Senior Software Engineer - DevOps Test Automation at Veritas Technologies
- Senior Software Test Engineer at Smiths Medical
- Senior QA Software Engineer at Code 42 Software
- Staff Software Engineer - Test Automation at QLogic
1 year, 10 months at this Job
- B.S.E. - Electrical Engineering
From Jan 2017 to present Position: Sr. Manager of DSP group / Voice interface Device Product Manager FORTEMEDIA Inc. focuses on developing high quality voice processing products (ASIC, Software, and system solution) My responsibilities are as: (1) VID (Voice Interface Device) SoC development (2) Hardware and software system architecture design, (3) Algorithm implementation; Hardware platform (ASIC) development Including (1) The high-performance microphone IC which supports two Mic sensors and provide the High SNR, High AOP, High Dynamic Range and Directionality features (Programmable Smart Microphone). (2) Voice processor SoC which integrates Multi-DSP core; ARM core and AI (Artificial Intelligence) hardware accelerator engine (Unified hardware accelerator for DNN, GRU, LSTM) for voice recognition, acoustic awareness and smart spectrum analysis application. VOS (Voice Operation System) software framework development VOS is the hardware independence Software framework and support either single core or multi-core DSP. It can dynamic manage memory, MIPS, power consumption; data buffer and framing; and algorithm executive. Used it can easily to plug in all kind voice processing, Voice Recognition, acoustic awareness algorithm (In-house and third party) through unified VOS API. From Aug 2013 to Dec 2016 Position: Sr. Manager of DSP group / Chief DSP architect (1) Research advanced DSP architecture to improve performance of in-house DSP and third party’s DSP IP (Tensilica, CEVA). Design optimal scheme for partitioning of hardware and software functions based on in-house specialized voice processing algorithms. (2) Development the always on the Smart Mic IC which is world fist smart Microphone solution. It is integrated AVD (Analog voice detection). Power consumption, Mic sensitivity and AOP can be configurable through I2C interface. The Smart Mic only need 50uA power consumption at always listen on standby mode. (3) Development Ultra-lower power Microphone Processor iM401 and iM501. This voice processor. This processor work with Smart Microphone will provide lowest power consumption VoW (Voice wake up) solution in the industry (Always listen on standby mode 50uA, Key phrase recognition 650uA) and the word class performance of Far Field Pick Up；Echo Cancellation；Noise Suppression with multi Mics Arrays processing (Beaming Forming；Blind Signal Separation) algorithm. (4) Improve team design, integration, system level verification and validate methodology. That include the system level verification with UVM; FPGA emulation platform; automated silicon validation platform (hardware, software, and scripts) build up and so on. (5) Provide internal technical training and external technical consultation.
- Sr. Manager of DSP group at Fortemedia Inc
- Manager of DSP group at ForteMedia (Nanjing) Co., LTD., Shanghai Branch
- Staff ASIC design Engineer at ForteMedia（Nanjing）, Co., LTD., Shanghai Branch
- Sr Driver and ASIC Verification Engineer at U.S.A. ForteMedia Shanghai Representative Office
5 years, 7 months at this Job
- Master's - Electronic Engineering
- Bachelor's - Computer Science
- Bachelor's - Mechanical & Automation engineering
- SR. R & D ENGINEER - II at Synopsys Inc
- R & D ENGINEER at IBM E & TS - Burlington
- R & D ENGINEER at IBM E & TS - Burlington
- R & D ENGINEER at IBM Global Services India Ltd
14 years, 2 months at this Job
- Master of Technology - Digital Electronics
Develop Robotic-Human Interaction (HRI) platform based on human work habits and practical scenarios, which enable robots to finish complicated capture and sealing tasks.
• Designed robotic work demo by AutoCAD with high precision robotic arc welder (IRB 1520ID) from ABB.
• Executed iterative experiments and let robot carry out task according to different predefined paths.
• Accumulated task finish time histogram by MATLAB and figure out the optimized execution method and algorithm.
- Electrical Engineer at UTC INSTITUTE OF ADVANCED SYSTEMS ENGINEERING
- ASIC Verification Engineer at DELTONE TECHNOLOGY INC
- Intern as Electrical Engineer at SMART GRID RESEARCH INSTITUTE
- Senior Design at SIMPLE DIGITAL VOLTMETER DESIGN BASED ON SINGLE CHIP MICROCONTROLLER
1 year at this Job
- Master of Science in Electrical Engineering - Electrical and Computer Engineering
- Bachelor of Engineering - design