• Responsible for the design of business circuits for our customers using met a solv
• Circuit ranging from 10gig down to dso. VOIP MPLS IPVPN, DIA, FLEX, PRI BBL etc.
• Primarily worked with Cisco routers and switches as part of the design.
• XO utilized DMS- 500 and alctel and adtran devices..
• Design internal transport expanding network
- Communication CIRCUIT DESIGN ENGINEER at XO
- Project Coordinator at XO Communications
- I/R Field Service Technician at Nextlink
- Analyst at Allegheny Health and Research Telecommunication Technical
13 years at this Job
Responsible for providing the most cost effective design solution, configuration,
equipment diversity and CLR/DLR accuracy within M6 and ASAP of all Windstream
New, MAC, and Disconnect customers, as well as network orders within the entire
• Train and assist junior Design team members in meeting performance objectives, as well as trained 4 Systems Engineers and 1 Data Implementation Engineer on the fundamental design process for full and partial voice and data customers, from OC12 and below.
- Circuit Design Engineer II at Windstream Communications
- Chief Petty Officer Electronics Technician at United States Navy Reserves
- Circuit Design / Systems Engineer at United States Navy Reserves
- NOC Technician at PAETEC Communications, Inc
7 years, 1 month at this Job
- B.S. - Network Management
- A.A.S. - Electrical Engineering Technology-Electronics
• Root cause modeling mismatches and improve design/modeling of performance, power and variation of future products based on Silicon measurements
• Assist other members of the global circuits team in design of circuit-based solutions for reducing system power and improving performance
• Work in a cross functional team in Silicon characterization and correlation to pre-Silicon Performance and Power models
• Apply circuit techniques to improve the power, performance and area utilization of the various communication link designs used in next generation GPUs
• Proficiency in scripting language, such as, Perl, Tcl, Make and automation methods/algorithms a certain plus
• Work as part of a global circuits team to design high speed data bus and communication links using Physical design tools
• Participate in cutting edge Processor design and debug in deep submicron technologies
- CIRCUIT DESIGN ENGINEER at Lifesize technologies
- Research and Teaching assistance at Texas A & M University
- India DESIGN VERIFICATION ENGINEER at Electronics Corporation of India Limited
- CIRCUIT DESIGN ENGINEER (INTERNSHIP) at Electronics Corporation of India Limited
7 months at this Job
- MS in Electrical Engineering - Electrical Engineering
- BTECH in Electronics and Communication Engineering - Electronics and Communication Engineering
Circuit Design: "Back-Bone" Cloud. Major larger Accounts.
- Circuit Design Engineer at CenturyLink
- Board Member, Superintedant, Vice President, Division Manager, Safety Manager, Foreman, Trainer Operations at AGUILA MINING
- Engineer at
20 years, 6 months at this Job
- Associate - BUSINESS, COMPUTER SCIENCE, Diesel, Wield advanced technology
- Hazardous Waist, Chemical Securment - BUSINESS, COMPUTER SCIENCE, Psychology
- Cyber Security - CYBER security
- Associate - BUSINESS, COMPUTER SCIENCE
- Some college
- Associate - BUSINESS
“Forensic Telecom” Compare telecom carrier and data center inventory database records against physical audit observations and revenue assurance sources to recommend action resulting in capital savings and new revenue opportunities.
- Circuit Design Engineer at ARM Data Center Solutions
- Team Lead - One Achord at Columbine Unity Spiritual Center
- Circuit Design Engineer Wavelength Services at CenturyLink
- Circuit Design Engineer - Private Line (ESA) Services at Level3 Communications
8 months at this Job
- Bachelor's - Astrophysics and Planetary Sciences
This position involved using Tirks to rearrange existing T1 circuits and upgrade them to the new ASR9K Router provided by Cisco. The systems used were hosted by CenturyLink. These included Apple, Core, and Tirks to complete the designs. These circuits utilized SONET rings as well as GigE 1-10
- Tirks Circuit Design Engineer at Cisco/CenturyLink
- Aircraft Dispatcher at Everts Air Cargo
- Circuit Design Engineer at Frontier Communications
- Activation Service Coordinator at Wavecom Solutions
6 months at this Job
- B.S. - Engineering
• Conducted over 200 special studies, projects and assignments in an effort to develop efficiencies for my employer as well as providing quality service to customers.
• Directed training and teaching several levels of telecommunications
• To new employees. Coached junior employees in time saving techniques, company policies and tips on efficiencies.
• Managed and monitored telephone conversations and assignments for 20 customer service representatives in a call center.
• Provided technical and procedural support for other departments within my company.
• Knowledgeable in Microsoft Excel, Access, Word and Visio.
• Have working knowledge of People Soft and Prism.
- Circuit Design Engineer at CCI, Roseville
- at Carrier Access/Local Number Portability Surewest
- Business Service Call Center Rep, Roseville Telephone at
20 years, 6 months at this Job
- BSN degree
L1 Instruction Cache (32KB, 4way set associated) on 10nm FinFet process technology ◦ Designed 16KB full custom dual power domain SRAM Array ◦ Ran extensive post layout Finesim simulations to check races, read, write margins ◦ Optimized macro power, timing. Worked closely with Physical designer to identify and fixed critical paths on chip level ◦ Analyzed EM/IR using Totem ◦ Worked with Physical Design Engineer to optimize Instruction Cache and Instruction Tag placements ❖ L1 Data Cache (32KB, 8way set associated) on 14nm FinFet process technology ◦ Worked with logic designer to come up with the high performance, low power Data Cache Array architecture ◦ Applied various circuit design techniques to ensure the macro work in wide range of voltages, frequencies ◦ Developed Vccmin simulation plan. Ran statistical simulations for process variations ◦ Ran equivalent checking (schematics vs RTLs) using ESPCV ◦ Planed and supervised layout ◦ Ran simulations to check all critical races. Optimized timing to meet frequency target ◦ Analyzed EM/IR using Totem ❖ L2 Tag Array (8way, 1024 entry, 25 tag bit) on 20nm process technology ◦ Designed high density SRAM hardmacro for large L2Tag Array ◦ Ran equivalent checking using ESPCV ◦ Planed and closely supervised layout ◦ Ran extensive post layout simulations to check races, read, write margins ◦ Optimized macro power, timing. Worked closely with Physical designer to identify and fix critical paths on chip level. ◦ Planned power switch placement ◦ Analyzed EM/IR (Totem) ❖ L1 Instruction cache (32KB, 8 way set associated ) on 28nm process technology ◦ Designed dual power domain 8T Array hardmacro ◦ Ran spice statistical simulations to ensure the macro can work at low voltage ◦ Placed and routed large Instruction cache softmacro using Magma ◦ Optimized area/timing for softmacro ❖ L1 Instruction Tag and Data Tag on 28nm technology ◦ Designed dual power domain 8T arrays ◦ Developed delay keeper logic to avoid read contention. Ran statistical simulations to ensure this worked at wide range of voltage corner ❖ Worked with Physical Design to floorplan, route and close timing for IU cache ( IU Data Array, IU Tag Array) ❖ Designed various voltage level shifters which are used in many arrays ◦ Static Voltage level shifter ◦ Dynamic Voltage level shifter ❖ Defined SRAM read/write margin methodology: ◦ Monte Carlo simulations to find weak read, write bitcell, senseamp mismatch ◦ Finesim to find read/write margins at all global corners with the weak read/write bitcells ❖ Full custom CAM: JTLB (level2 TLB) 32 entries, 20 bits ◦ Designed 32 entry x 20 bit CAM ◦ Ran equivalent check using espcv tool ◦ Planned and supervised layout ◦ Optimized timing ❖ Silicon Debug for high Vcc low yield for Snapdragon processor in 20nm technology ◦ Worked with validation engineers to run test vectors, analyze shmoo plots to identify design weakness. ◦ Worked with the designer to simulate to reproduce failures ◦ Proposed design fixes ◦ Updated silicon showed no yield loss ❖ Silicon Debug for low Vccmin yield for Snapdragon processor in 14nm technology ◦ Process off target causing yield hit on our SRAM memories at low voltage ◦ Worked with the design engineer and validation engineers to find the root cause ◦ Proposed circuit fixes ◦ Updated silicon showed no yield loss
- SRAM Circuit Design Engineer at Qualcomm
- Custom Circuit Design Engineer at Sun Microsystem
- Custom Circuit Design Engineer at Motorola
14 years, 2 months at this Job
- BS - Electrical Engineering
of Bus Integrated Power Controller unit. . Unit engineer for the 30V Low Voltage Converter (2500W) . Unit responsible engineer for the 50V & 100V Bus Integrated Power Controller units . Circuit design / Unit Engineer for NSP's 30V Bus Down Converter Unit (3200W) . Circuit design / Unit Engineer for ODIN's 30V Bus Voltage Limiter (BVL) . Responsibilities: Circuit design issue and modification. Worst-case circuit performance analysis using Pspice and Simetrix modeling. Perform FMEA/FMECA. Perform stress and derating analysis. Support test production. Support unit EMI test. Support spacecraftpower converter anomaly failure.
- Circuit responsible engineer for new generation at Boeing Satellite System
- Engineer Scientist at Boeing Satellite System
- Circuit design / Unit engineer at Boeing Satellite System
- Circuit Design / Unit Engineer for SSPA at Boeing Satellite System
21 years at this Job
- certification - Power Electronics I
- Circuit Design Engineer at Aureon
- Field Engineer at Phoenix Telecom
- Circuit Design and Provisioning Engineer (Promoted) at Windstream
- Circuit Design and Provisioning Engineer (Promoted) at AT&T
1 year at this Job
- Certification - Telecommunications Technical Specialist
- Certification - A Plus
- High School Diploma
- MapInfo Certification - Visio Traning
- Fiber Optics and RF Certification - Fiber Optics