Responsibilities ▪ Assist USB Type-C design team to design digital blocks using Verilog and System Verilog (Cadence NCSim and RC) ▪ RTL design of new and reusable digital blocks, parameterize them, create test benches, assertions and documentation. ▪ RTL for MMIO bridge Registers, CDC, Interrupt generation, run Formal verification and Synthesis.
- Digital Design Engineer Intern at NXP Semiconductors USA, Inc.
- Digital Design Engineer Intern at Microchip Technology Inc
3 years, 5 months at this Job
- MSE - Electrical Engineering
- Advance Diploma In ASIC Design - ASIC VLSI Design
- Bachelor of Engineering - Electronics and Telecommunication
* Optimized and merged behavioral model of analog block in SystemVerilog * Checked functional equivalence between behavioral model and analog block with amsDmv * Explored designing 3rd order digital filter in MATLAB and Verilog * Measured chip power consumption with MATLAB-aided in validation lab
- Summer Intern - Digital Design Engineer at CIRRUS LOGIC
3 months at this Job
- Master of Science - Integrated Circuits and System
- Bachelor of Science - Microelectronics Technology
- Physical layer (PHY) hardware modeling, algorithm development and performance evaluation. Developed floating-point / fixed-point models (C / C++ / Matlab) for Wi-Fi 802.11ac/ax Physical-Layer (PHY) hardware (HW) implementation. Models are used as golden reference for Design Verification (DV) as well as performance characterization and final performance sign-offs. Developed large-scale automation tools and testing environment for code-quality assurance and performance characterization for end-to-end PHY models. Identified performance deficiencies and proposed enhancements to PHY algorithms and implementation. Worked closely with Standards, Design and Verification teams to ensure timely deliveries of models and verified designs.
● Wi-Fi PHY algorithm & systems design
● Translated system requirements into engineering specifications
● Presented appropriate system architecture
● Designed floating-point C/C++ PHY simulator
● Designed fixed-point C/C++ hardware model
● Hardware friendly algorithm development (Equalizer, Symbol Demapper, Symbol Processor, etc.)
● Bit-true test vector generation and RTL bit-matching
● Built large-scale automation systems for performance evaluation (regression test environment)
● Lab prototype bring-up experiences
● Worked with geographically distributed teams Digital Design Engineer - Digital design preferably in physical layer (PHY) baseband design. Good understanding of verification methodologies and languages. Developed 2-stream MIMO symbol detector for Wi-Fi system.
● Developed low-complexity near-optimum algorithm
● Designed floating-point model
● Designed hardware-friendly fixed-point model with optimized bit-widths
● Defined & documented appropriate block architecture
● Implemented RTL model with Verilog HDL and integrated into the overall system
● Designed block level tests
- Wireless Systems Engineer / Digital Design Engineer at Samsung Electronics
6 years, 10 months at this Job
- PhD - Electrical & Electronic Engineering
- MS in Electrical - Electrical & Electronic Engineering
- BS - Electrical & Electronic Engineering
RTL design for aviation transponder and rangefinder.
• Designed, debugged, and documented several logic blocks for an FPGA-based on-board, low-power, low-volume aviation rangefinder. Later did the same for an aviation transponder in the same package
• Submitted an invention disclosure for a novel mesochronous synchronization solution.
• Aided the FAA certification effort for the transponder.
• Mentored several less-experienced logic design engineers. Received strong reviews for my efforts. Reference available.
• Authored the RTL coding guidelines for the company also to strong reviews.
- Senior Digital Design Engineer at Sagetech Corporation
- Staff Digital Design Engineer at Lattice Semiconductor
- Senior Component Engineer at Intel Corporation
- at Intel Corporation
2 years at this Job
- Bachelors of Science in Electrical Engineering - Electrical Engineering
Responsible for integration of various Hard and Soft IPs into a PCIe-attached accelerator using Synopsys coreTools. Study the subsystems high-level / micro architecture specifications, learn Synopsys coreTools, implement glue logics, etc
- Senior Digital Design Engineer at Intel
- Senior Digital Design Engineer at Qualcomm
- DFT/ Digital Design Engineer at ATR International
- Senior ASIC Digital Design Engineer at Silicon Image
5 months at this Job
- Bachelor of Science - Computer Engineering
Integrated Processing Computer (IPC-8310) Project:
The IPC-8310 is a mission computing, network data management and video switching functions proven in the most rugged military helicopters and fixed wing aircraft.
• Designed an Ethernet Switch Board which includes: ✓ Xilinx FPGA Zync Ultra Scale MPSoCs ✓ Microsemi Ethernet Transceiver, Ethernet data rate 10/100/1000 is Mbps ✓ Cisco Fiber Optic Transceiver, A Serializer/Deserializer (SerDes) data rate is 10Gbps
• Designed an Ethernet Switch Board FPGA which includes: ✓ Ethernet Layer 1 (QSGMII) IP ✓ Ethernet Layer 2 (Tri Mode Ethernet Mac) IP ✓ Ethernet Switch
- Lead Digital Design Engineer (Contract) at Rockwell Collins
- Lead Digital Design Engineer (Contract) at Zin Technologies
- Lead Digital Design Engineer (Contract) at Raytheon
- Lead Digital & Analog Design Engineer (Contract) at Freelance at FPGA Design
10 months at this Job
- Bachelors of Science in Electrical Engineering - Electrical Engineering
Santa Clara, CA August 2011- Present
Result Orientation Digital Design Engineer
Strong Initiative Taking
• Xeon Server CPU team player with successful tape-in experience of 14nm and pathfinding experience for 14nm/10nm design methodologies.
• Feature Lead for the scan chain test architecture and responsible for scan SKILLS auditing and power budgeting.
• Owned 3 mega-blocks of the section and performed RTL-to-Synthesis Netlist Physical Design generation, Place & Route, Clock Tree Synthesis to deliver timing and DRC converged design. Schematic Design
• Analyzing physical design quality and engaging with Design Automation, RTL Electronic Design Automation partners and cross-functional forums to achieve power and utilization targets.
• As an Intel Innovation team member, experimented with automatic placement Engineering Change Order of hard macros to enable design leverage in System on Chip (SoC) projects. Design convergence
- Digital Design Engineer at RECOGNITION
- social entrepreneur at Arduino
- Social Media Coordinator at IoT Un-Conference
- PCB Design Intern at Alaris
7 years, 5 months at this Job
• Design/Verification - FPGAs/CPLDs - Xilinx/Altera - VHDL - Vivado/Quartus Prime - ModelSim/QuestaSim ◦ ADC's, Memory, Message Routers, timing analysis, IFC, I2C, SPI, UART, Ethernet, PCIe, DDR4, Controllers
• Hardware debug in lab environment using a variety of equipment such as: ◦ Oscilloscope, Spectrum Analyzer, Power Supplies, Function Generator, Multi-Meter, Soldering
• Wrote technical documents viewed by the customer such as Hardware Requirements and Design/Verification Documents
- Digital Design Engineer at Northrop Grumman
- UCSD Researcher at Northrop Grumman
- Product Reliability Engineer at Hunter Industries
4 years at this Job
Vector co-processor - ASIC design and implementation, that include design specification, RTL coding, synthesis, LEC, simulation verification, of a 16-bit integer/32-bit floating-point vector pipeline co-processor for an embedded touch processing system in 55 nm process and clock speed of 250 MHz. The co-processor supports integer and single-precision floating-point operations, with a dedicated convolution and FFT engine, is capable of 250 MFLOPS, and is well-suited for implementing various digital signal processing algorithms. ⋅ Instruction cache - design and implementation of a 16-K bytes direct-mapped and 2- way set associative instruction cache. ⋅ Digital-analog frontend implementation and evaluation. Work with the architecture team to evaluate different DSP algorithms and the impact on silicon area and power consumption. ⋅ Serial test port - design and implementation of a serial test port with propriety protocol and configurable bus width that connects the tester to the embedded processor ⋅ ASIC prototyping of embedded touch controller with Xilinx Virtex-6 FPGA for hardware firmware/software co-development.
- Senior Staff Digital Design Engineer at Synaptics, Inc
- Senior Staff Design Engineer at Xilinx, Inc
- Distinguished Member of Technical Staff at Mahi Networks, Inc
- ASIC Design Engineer at Fujitsu Network Communications, Inc
7 years at this Job
- PhD - Electrical and Computer Engineering
- - Electrical and Computer Engineering
- BSc - Electrical Engineering
for their analog and mixed signal product line. Supported multiple accounts and the job duties evolved into doing custom layout and verification for the product lines at the chip level and below all the way through final delivery of gds. Also supported the test group with digital design using Altera FGPA to create a bit rate tester for a DVI interface. Pivotal was bought by Broadcom in early 2000 and duties expanded to managing a layout group and producing several chips for Broadcom utilizing the DVI interface designed at Pivotal. Then worked primarily as a digital design engineer to help transition DVI to HDMI and worked on digital design aspects of that interface and others until 2004. Transferred to the physical IC group doing P&R using various tools (latest one was Innovus). Duties involved interfacing with the frontend design and synthesis engineers to take a gate level netlist through P&R to a timing clean and physically verified product. This was typically a block/blocks incorporated into a chip but was also responsible for several chips as well. All would require various levels of floorplanning and ECO implementations until project completion.
- product engineer at Pivotal/Broadcom
- Technical sales at Norcomp SoCal
- field applications engineer at ComCore/National Semiconductor
- Field applications engineer supporting the ORCA FPGA product line at AT&T/Lucent Technologies
19 years, 2 months at this Job