Chandler, AZ Feb 2017 - Present
Maxim Integrated designs and manufactures analog and mixed-signal ICs in the automotive, industrial,
communications, consumer and computing space.
Digital Design Engineer, Automotive Business Unit
• Design, Simulation and Validation of Digital Logic for Power and Battery Management ASICs.
• Assisted with the design and validation of Maxim's flagship battery management IC. This ASIL-D compliant IC measures 14 cell channels using a 16-bit SAR ADC.
- Digital Design Engineer, Automotive Business Unit at Maxim Integrated
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2 years, 4 months at this Job
- Masters of Applied Leadership and Management
- Master's - Electrical Engineering
- Bachelor's - Electrical Engineering
RTL Design/Verification/Validation of Xilinx UltraScale FPGA for DDR4 IO Buffer with AXI in the HybriDIMM (DIMM + NAND Flash Memory). Design of RTL and Algorithm for Slave IO (DDR4 DRAM PHY Interface) Train/Calibration to work properly in the high performance in the HybriDIMM. Verilog Design and Implementation to Xilinx Ultra Scale using Vivado tool and Debug/Lab bring up with ChipScope and ILA (Integrated Logic Analyzer). Static Timing Analysis and Timing Constraint design to meet the timing budget of FPGA. Simulation/Verification of the Slave IO (DDR4 PHY and IO Buffer) using Mentor Modelsim/Questa. Design of BCOM Bus Control of DB (Data Buffer) in the HybriDIMM(LRDIMM Compatible).
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• Design of application oriented/customer-driven Ethernet IPs - 10G MAC, 40G MAC, QoS.
• Developed Verilog code for designing the specific features of project and basic verification using Verilog Testbench. Worked on basic Synthesis (DC compiler) and Spyglass (CDC/Lint) tools to validate efficiency of code in MAC.
• Prepared and reviewed documentation of the deliverables and worked as a team to successfully deliver multiple EAs and 3 main GAs. Delivered a Technical presentation to the SG-IP managers and peers on Internet of Things-IoT.
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RTL Design, Test and verification of FPGA for Distributed Antenna System (DAS) Repeaters. Implementation of Common Public Radio Interface (CPRI), RF Filtering, Mixers, Memory Interfaces, AXI (AMBA) Interface and Registers.
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- - M.Sc.Eng System-on-Chip Design
- B.Sc - Electrical-Electronic
• A RF Engineers and Analog and Digital Design Engineer Company.
• Used various tools professionally.
• Capable of design and repair of satellite antenna and satellite receivers, telecommunication and video and music equipment.
• Installed and adjusted the satellite antenna placement. RESUME
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- license - training
- H. S. Diploma
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- BS - Electronics & Telecommunication Engineering
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- Bachelor of Science
• Responsible for FPGA design and verification using SystemVerilog and Universal Verification Methodology (UVM).
• Responsible for creation of Design and Verification specifications.
• Support Design Assurance Department by performing FPGA Design Reviews.
• Experience with current generation FPGA devices: Zynq SoC, Virtex 7, Ultrascale
• Experience with using Xilinx High Level Synthesis (HLS) for implementing image processing functions.
• Utilize Real Intent’s Lint and Meridian CDC tools in support of high QoR designs
• Experience with integrating in the lab with software engineers in an embedded system and Hardware-in-the-Loop setups.
• Extensive debugging experience with Xilinx Hardware Manager, and SDK.
• Experience with configuration management systems: Razor, AccuRev, Git, Jira.
• Experience with security applications and associated Validation & Verification process and execution.
• Experience with TCL and shell scripting in support of automated FPGA build flows.
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- Master of Business Administration - Discounted Cash Flow Analysis for Business Expansion
- Master of Engineering - Wireless Communications
Working in a clean-room environment Involved in JPSS ATMS Receiver Subsystem Project. Testing waveguide modules of microwave frequency multiplier, DRO and PLO (Phase Lock Loop Oscillator), Amplifier with detector, External Harmonic Mixer of K-Band, V-Band, and W-Band. Also including overall system analysis, system integration/testing.
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