ASIC Physical Design & Physical Verification | BWI
o 8x9mm Global Foundries 14LPP-XL technology ASIC
o Designed & deployed MiMCAP leveraging Cadence Virtuoso custom layout editor
o Executed DRC and LVS for IP and block verification, including scripting and optimization o Successfully "Taped Out" design and worked with the foundry to provide waivers
o Stood up Physical Verification Methodology for a government classified project
o Awarded 3 Department awards for efficiency and finishing ahead of schedule
• Digital Design Engineer | San Diego o Lead firmware designer on Kintex 7 devices. o Maintained Git Repository and provided daily status during scrum meetings o Responsible for documenting Top Level Architecture Design o Incorporated new algorithms in current infrastructure o Trained new digital designers on current design o Enhanced test bench environment using OSVVM o Awarded 2 department awards for taking on a stretch assignment
• Systems Engineer Integration & Test | San Diego o Verified performance specifications by conducting system and sub-system Acceptance Test Procedures o Resolved numerous software and hardware issues using system documentation and basic troubleshooting o Awarded 1 department award for delivering to the customer on time given the technical difficulty
• CCA Test Engineer | BWI o Prepared a Design Verification Test and documentation for the prototype TRVS board o Learned how to configure and program the FPGA using the Xilinx Tool o Developed an IBERT verification for the TRVS SERDES o Collaborated with Fellow engineers and Vendor (VECTRON) to work through a discrepancy in the design implementation
- Digital Design Engineer at Northrop Grumman Corporation
2 years, 7 months at this Job
- BS in Electronics Engineering - Computer Digital Systems
RF Audio Chip (2018-2019)
• Spec'ed and designed an on-chip diagnostic block that can simultaneously capture RXADC data and send TXDAC data, with programmable triggers, capture rates, delays, etc
• Owned the PHY, an existing design, by handling integration, upgrading the bus interface to 32-bits, and making changes to the PTM's firmware microcode
• Overhauled the digital-analog interface, including a more refined way for PUP sequencing components of the analog blocks, and scripting a way to verify connectivity along the interface
• Wrote a script to automate gate-level simulations with back annotated timing across all corners, including balancing server load, a process that was previously manual and laborious
• Built a fully bootstrapped toolchain (assembler, linker, compiler) using the latest version of Glibc for the kernel on our servers that run a 10+ year old version of Linux to support Cadence's IC5. This allowed us to compile newer versions of software on these servers
- Principal Digital Design Engineer at Avnera / Skyworks Solutions
- Software Developer at Rigelsoft
- Principal Digital Design Engineer at Intel Corporation
- Senior Design Engineer (only 3 levels at Linear) at Linear Technology Corporation
1 year, 2 months at this Job
- Bachelor's - Electrical and Computer Engineering (4.0 major GPA, 3.96 cumulative GPA)
- Minor - Japanese
Vector co-processor - ASIC design and implementation, that include design specification, RTL coding, synthesis, LEC, simulation verification, of a 16-bit integer/32-bit floating-point vector pipeline co-processor for an embedded touch processing system in 55 nm process and clock speed of 250 MHz. The co-processor supports integer and single-precision floating-point operations, with a dedicated convolution and FFT engine, is capable of 250 MFLOPS, and is well-suited for implementing various digital signal processing algorithms. ⋅ Instruction cache - design and implementation of a 16-K bytes direct-mapped and 2- way set associative instruction cache. ⋅ Digital-analog frontend implementation and evaluation. Work with the architecture team to evaluate different DSP algorithms and the impact on silicon area and power consumption. ⋅ Serial test port - design and implementation of a serial test port with propriety protocol and configurable bus width that connects the tester to the embedded processor ⋅ ASIC prototyping of embedded touch controller with Xilinx Virtex-6 FPGA for hardware firmware/software co-development.
- Senior Staff Digital Design Engineer at Synaptics, Inc
- Senior Staff Design Engineer at Xilinx, Inc
- Distinguished Member of Technical Staff at Mahi Networks, Inc
- ASIC Design Engineer at Fujitsu Network Communications, Inc
7 years, 2 months at this Job
- PhD - Electrical and Computer Engineering
- - Electrical and Computer Engineering
- BSc - Electrical Engineering
RTL Design, Test and verification of FPGA for Distributed Antenna System (DAS) Repeaters. Implementation of Common Public Radio Interface (CPRI), RF Filtering, Mixers, Memory Interfaces, AXI (AMBA) Interface and Registers.
- Digital Design Engineer at Maven Wireless
- FPGA Design Engineer at Axis Communications
- Methodical Verification of FPGA design at ABB Robotics
- Instrument and Control and IT Engineer at KPIC, Kermanshah Petrochimical Company
1 year, 11 months at this Job
- - M.Sc.Eng System-on-Chip Design
- B.Sc - Electrical-Electronic
High Reliability aviation systems, redundant protocol and architecture development, DO254 qualifiable. Automotive position/angle Sensors: System on a chip, mixed signal ASICs. ISO262626 and ASIL B qualified. Architected and designed and digital filters, jtag test access ports, watchdog, xbar, memory controllers, clock generation, error detection and correction in serial ports. Integrated peripherals and other logic IPs into our SOC mixed signal ASIC. Prototyped on Xilinx FGPA board. Extensive verification, both with HDL and annotated netlists, some mixed signal modeling at system level.
- Senior Digital Design Engineer at Microsemi/Microchip
- at Microsemi/Microchip
- Executive oversight for ThermalRiders Marketing, Sales and Flight Operations at All Ben Dunn Design and Consulting
- Digital Design Engineer at RF Micro Devices
5 years, 1 month at this Job
- B.Eng. - Electrical and Electronic Engineering B.Eng
- - C, Critical Thinking, Discrete Time Signal Processing
Worked under Dr. Kevin Camera, director of firmware engineering
● Advanced capabilities for analysis and storage of ADC data by developing a 6,000+ line Python package, improving firmware bring-up speeds and facilitating robust signal analysis.
● Created framework for retrieving the stored ADC data within QuestaSim following UVM using SystemVerilog, where queries can select specific real-world signals and input them into the testbench.
- FPGA Digital Design Engineer Intern at Velodyne LiDAR, Inc
- Teaching Assistant at Georgia Institute of Technology
- Systems Engineer Intern at Georgia Tech Research Institute
3 months at this Job
- M.S. - Electrical and Computer Engineering
- B.S. - Electrical Engineering
• Developed an IP responsible for Power, Reset and Clock management ("PRCM") of an Automotive Infotainment Product line SoC (28nm technology) in a rapidly changing and fast paced environment
• Integrated PRCM with several other IPs within the SoC and upgraded necessary interfaces of certain IPs to meet standard SoC requirements specifications
• Developed and managed register and memory-map infrastructure of PRCM IP using Socrates BitWise tool
• Performed Clock Domain Crossing checks on RTL & Implemented ECOs in Logical Synthesized netlist
• Automated test case generation process for verification using PERL
• Drafted IP design documents, functional & register specifications and product technical reference manuals for the SoCs in my ownership
• Collaborated with Verification, DFT and Physical design teams and Architects to understand project requirements and delivered projects on time
- Digital Design Engineer at Texas Instruments
- CAD Engineer at Microchip Technology
- Verification Intern at ST-Microelectronics
2 years at this Job
- M.S - Electrical Engineering
- M.S - VLSI-CAD
- B.E - Electrical Engineering
Designed fonts, performed machine maintenance, organized shipping and receiving, satisfied customers with outstanding customer service.
- Digital Design Engineer at DSD Embroidery
- Freelance Audio Engineer at Tri
- Guitarist at Slick Idiot
- Guitar Instructor at Relic Radiation
14 years, 2 months at this Job
- - general
• Digital design engineer on a mixed-signal power management device.
• Designed three Verilog modules and simulated with Cadence’s Incisive simulator.
• Created a multi-device simulation testbench to simulate a new communication block. · Developed a Python based ARM cortex M0+ device emulator to allow pre-silicon debugging of embedded ROM code. Simulates code from the Keil tool set.
• Developed ROM code to program/erase flash memory.
• Developed Python digital signature analysis to validate battery pack authenticity.
• Developed a Python based Verilog code generator for a register file from an XML description.
• Wrote a Python script to generate Verilog AMS interface modules.
• Wrote Python script to analyze device parasitics to quantify noise in a new mixed-signal device.
- Digital Designer/Embedded Firmware Developer/Python Scripter at Texas Instruments (contract through Talent 101)
- VP Engineering at AMS/Texas Advanced Optical Solutions
- VP/GM at Broadcom Corporation
- Director of PQ3/PQ4 Operation at Motorola Semiconductor/Freescale Semiconductor
2 years, 6 months at this Job
- Bachelor's - Electrical Engineering
RTL design for aviation transponder and rangefinder.
• Designed, debugged, and documented several logic blocks for an FPGA-based on-board, low-power, low-volume aviation rangefinder. Later did the same for an aviation transponder in the same package
• Submitted an invention disclosure for a novel mesochronous synchronization solution.
• Aided the FAA certification effort for the transponder.
• Mentored several less-experienced logic design engineers. Received strong reviews for my efforts. Reference available.
• Authored the RTL coding guidelines for the company also to strong reviews.
- Senior Digital Design Engineer at Sagetech Corporation
- Staff Digital Design Engineer at Lattice Semiconductor
- Senior Component Engineer at Intel Corporation
- at Intel Corporation
2 years at this Job
- Bachelors of Science in Electrical Engineering - Electrical Engineering