Principal level FPGA engineer designing video systems. * Build FPGA designs on ZYNQ Ultrascale+ platform for data collection. 10M/100M/1G ethernet MAC/DMA design. CAM/TCAM design to support address based flows. Generate/update C code in Xilinx SDK to support platforms (ARM Cortex/Microblaze).
- FPGA Design Engineer at Blue Origin
- Principal FPGA Design Engineer at Astronics CCC Inc
- Principal FPGA Design Engineer at Pivotal Commware Inc
- Principal FPGA/ASIC Design Engineer at Ossia Inc
8 months at this Job
JUICE RIME and REASON spacecraft instruments. Design of HF and VHF receivers and class- D PAs, and switch-mode power supplies for ice-penetrating radar applications. These are
implemented using discrete transistors and custom magnetics for lowest power consumption while remaining operational in a high-radiation environment. Extensive board-level
electromagnetic stimulation was performed in AWR Microwave Office to augment lab
development and to facilitate migration to board layout.
• PLASMIC spaceflight instrument algorithm and implementation in a Microsemi ProASIC3 FPGA. Digital signal processing functions (pulse shaping, baseline restore, and peak detection) are implemented to count and classify particles.
• High-Granularity Timing Detector (HGTD) in ATLAS at the CERN LHC. System design of a detector system requiring a readout of nearly 2 million sensors with a 30 ps time resolution.
- RF and FPGA design engineer at University of Iowa, department of Physics and Astronomy
- Sr. Design Engineer at University of Iowa, Department of Physics and Astronomy
- Senior digital signal processing design engineer at Softronics Ltd
- Senior Digital Signal Processing Engineer at Rockwell Collins
3 years, 1 month at this Job
- BSEE - electrical and computer engineering
• Responsible for FPGA design and verification using SystemVerilog and Universal Verification Methodology (UVM).
• Responsible for creation of Design and Verification specifications.
• Support Design Assurance Department by performing FPGA Design Reviews.
• Experience with current generation FPGA devices: Zynq SoC, Virtex 7, Ultrascale
• Experience with using Xilinx High Level Synthesis (HLS) for implementing image processing functions.
• Utilize Real Intent’s Lint and Meridian CDC tools in support of high QoR designs
• Experience with integrating in the lab with software engineers in an embedded system and Hardware-in-the-Loop setups.
• Extensive debugging experience with Xilinx Hardware Manager, and SDK.
• Experience with configuration management systems: Razor, AccuRev, Git, Jira.
• Experience with security applications and associated Validation & Verification process and execution.
• Experience with TCL and shell scripting in support of automated FPGA build flows.
- Staff ASIC & FPGA Design Engineer Clearance at Lockheed Martin Inc
- Digital Design Engineer II, Clearance at Exelis Inc
- Electrical Engineer, Clearance at BAE Systems Inc
- Electrical Engineering Intern at ITT Exelis
6 years, 3 months at this Job
- Master of Business Administration - Discounted Cash Flow Analysis for Business Expansion
- Master of Engineering - Wireless Communications
- Developing image pipeline algorithm (RGB to RBGW) using Matlab. - Developed Verilog RTL code for the algorithm. - Developed and Improving FPGA codes for TCON for Electro-Wetting Display with HDMI, LVDS interface. - Implement, Synthesis, Timing Closure, Simulation and generate bitmap to Xilinx Zynq 7000 SoC reference kit and Ultra Scale Zynq -ZCU102 SoC reference kit and Intel FPGA. - Writing Python scripts for generating graphic images and controlling demo system. - Developing application C code of Uart, DMA, I2C using Xilinx SDK. - Lab hands-on experiments and debugging with Logic Analyzer, Oscilloscope. - Languages: Verilog, VHDL, C, Matlab, Python, Tcl - FPGA tools: Xilinx Vivado, Intel Quartus II, ModelSim. - Interface: HDMI RX/TX, I2C, SPI, AXI4, APB. - OS: MS Windows, Linux. - Version control: GIT.
- Sr. FPGA design engineer at Clearink Displays Inc
- ASIC verification engineer-contract at Amazon Lab126
- Pixel IP RTL design contract (Off-site) at Google
- RTL design engineer-contract at Samsung Display Lab
1 year, 10 months at this Job
- Master's - Electrical and Electronic Engineering
- Bachelor's - Electrical and Electronic Engineering
at this Job
• Designed Kintex Ultrascale FPGA with 40G Ethernet interface connected to ADCs and DACs. FPGA maps incoming Ethernet MAC/UDP addresses to AXI4 channels and AXI4 channels to outgoing MAC/UDP addresses.
- FPGA Design Engineer at Xlera
- Senior Hardware Design Engineer at QUSTREAM
- Senior Hardware Design Engineer at FORTEL DTV
- Digital Hardware Design Engineer at DIGITAL VIDEO SYSTEMS
5 months at this Job
- B.S. - Electrical Engineering
Worked with a design team to develop next-generation CPU and SOC designs for the Devices Development Group, including micro-architecture, IP integration, circuit design, and timing convergence. Ran Synopsis ICC2 checkers and a proprietary clock simulation tool on physical clock routes on DDR, MEMS, and SOC designs; Fixed any issues that arose by correcting the layout. Reviewed the results of the clock tool, then developed possible solutions for high skew and high delay clock routes. Migrated proprietary scripts to create physical routes from Verilog inputs in support of next generation designs. Developed front-end Python-based web tool for visualizing outputs of clock simulation and routing path simulation tools to enable faster and more efficient routing analysis.
Worked with a design team to develop next-generation CPU and SOC designs for the Devices Development Group, including micro-architecture, IP integration, circuit design, and timing convergence.
Ran Synopsis ICC2 checkers and a proprietary clock simulation tool on physical clock routes on DDR, MEMS, and SOC designs; Fixed any issues that arose by correcting the layout.
Reviewed the results of the clock tool, then developed possible solutions for high skew and high delay clock routes.
Migrated proprietary scripts to create physical routes from Verilog inputs in support of next generation designs.
Developed front-end Python-based web tool for visualizing outputs of clock simulation and routing path simulation tools to enable faster and more efficient routing analysis.
- ASIC/FPGA Design Engineer (Summer intern) at Intel
- Systems Engineer at Forsythe Engineering
- Electrical Engineer (Year-round intern) at Ultra Electronics USSI
- Electrical and Computer Engineer (Summer Intern) at Raytheon
4 months at this Job
- Bachelor's - Electrical Engineering, minor in Math; Computer Engineering, minor in Computer Science
Consulting Engineer (Azad, Inc) to Tektronix Corporation VPL group 14150 SW Karl Braun Dr Beaverton, OR 97077 Calypso project: The Calypso project is a large FPGA based design intended to monitor multiple MPEG video streams and report error rate in a real-time or recorded video environment. My tasks were interfaces to program 4 Virtex-5 FPGAs from a PCIe interface in a PC. I coded, simulated, and tested the FPGA bit file loaders with data provided by the PC and stored in local DDR2 SDRAM memories. I also designed the SPI, I2C, and one-wire interface controllers for communications with small monitor and clock control chips on the board. TG700 HDVG7 project: The HDVG7 is a module of the TG700 television sync generator system. The HDVG7 logic is contained in an Altera EP2S60 FPGA. HD digital 3GHz serial streams are generated in most worldwide HD formats for distribution throughout a TV studio, test signals are also used for OEM equipment testing. The video stream contains digital values for video, audio, and time code data sources to be used by downstream equipment. Tasks performed: Designed and programmed digital video stream packet insertion engines to allow arbitrary packets of SMPTE minimum up to maximum size anywhere in the video frame for HD video formats. Designed and programmed SMPTE ANC LTC timecode for HD, programmable audio NCO sine wave generation and packetizing for up to 32 independent embedded audio channels. Supported other FPGA designers using the Altera Quartus FPGA design software. All programming code was done in Verilog. TG700 GPS7 project: The GPS7 is a module of the TG700 providing very accurate analog television sync signals for studio timing references. Signals generated are: 3 analog TV sync, 4 analog LTC audio frequency timecode reference sources. The GPS7 incorporates a complete GPS receiver to extract very precise GPS based time reference to lock the local TG700 reference clock, from which all other TG700 sync signals are derived. The GPS7 contains 3 programmable logic parts: MAXII glue chip for processor IO, EP2C5 for the GPS control and clock PLL, EP2C35 for the video and LTC generators. Outputs of the EP2C35 drive video and audio DACs. Tasks performed: Designed the GPS7 module in Cadence Allegro. Designed and coded FPGAs, re-using significant preexisting IP for the video format generators. Designed and coded the LTC timecode generators and wave shaping for valid audio spectrum outputs using a dedicated audio multichannel DAC. Re-used existing designs for the video generators, modifying the original design to eliminate all manual adjustments (potentiometers) by the use of DAC gain and offset analog controls, allowing automated calibration with bench equipment at manufacture. Designed a 1 Hz PID controlled PLL, locking the TG700 54 MHz reference clock to the GPS 1PPS pulse to within 15 ns of 'absolute' time. Designed a charge pump circuit to compare the 1PPS from the GPS module to a local 1PPS from the 54MHz clock to get an accurate (within 0.384ns) error, which combined with the total calculated quantization error from the GPS module was used to steer the 54MHz OCXO in the TG700 mainframe for very precise time reference. Co-developed timing mechanisms in hardware and software to establish television sync signals referenced to the SMPTE epoch of Midnight January 1 1958, something the TG700 was not originally designed to do. Modified legacy TG700 modules to incorporate timecode in support of the GPS7 project. Developed many testing mechanisms for timing verification of the GPS7 and legacy modules.
- Senior FPGA Design Engineer at Azad, Inc
- Senior FPGA Design Engineer at Azad, Inc
- Senior FPGA Design Engineer at Oxford, Inc
- HW/SW Design Engineer Contractor at Signum Systems Corporation
3 years, 7 months at this Job
- no degree - Mechanical Engineering
• Developed a CAN Node FPGA that interface to CAN Router via SSL's Control Area Network (CAN) buses.
• Integrated 2x CAN controller IP (VHDL module) for redundancy design requirement.
• Implemented Bus Interface logic to access entire memory mapped registers of the CAN Controller via the AMBA 2.0 APB bus. Implemented APB Arbiter to arbitrate requests from Tlm-Tx, Msg-Poll, Loopback, Cmd-Ack, Err-Stat, and CAN-Init blocks.
• Implemented SPI Bus Interface blocks to drive off chip DAC's and ADC via two separate SPI ports.
• Implemented EEPROM Interface block to access external EEPROM for chip initialization during power up.
- FPGA Design Engineer at Space System Loral
- FPGA Design Engineer at LG Electronics
- Design Consultant at Sintegra Design Services
- FPGA Design Engineer at Space System Loral
10 months at this Job
- M.S. in Electrical Engineering. - Electrical Engineering
• Developed and delivered complete IP, wrote from specs finalization to FPGA proto-type targeted on Xilinx Virtex UltraScale, including functional specs documentation, RTL, simulations, synthesis, back-end timing and lab bring-up.
• Collaborated with the Secure team to design, implemented and successfully launched the first secure boot FPGA design in BU.
• Developed, tested and integrated complex FPGA code for high-performance inspection systems with minimal supervision.
• Debugged chip level and module level FPGA RTL simulations to find functional bugs.
• Created test cases and developed test-bench and test plan in System Verilog with VMM to verify design against design specs.
• Verified designs which wraps Xilinx IP based design, i.e. CAUI, SerDes.
• Reported coverage including functional, code and other metrics.
• Constrained Random Verification with SystemVerilog using VMM and UVM.
- FPGA Design | Design Verification Engineer, CA at CISCO SYSTEMS
- FPGA Design Engineer, CA and TX at CISCO SYSTEMS
- Research Assistant, Electrical Engineering at UNIVERSITY OF NEW BRUNSWICK
4 years at this Job
- Master of Science - DSP
- Bachelor of Science - BS, Electrical Engineering