• Working as Digital IC Design Engineer for Device Architecture Group.
• Designed digital sections on RF-to-Baseband Transciver IC. Digital sections included blocks such as AGC, SPI protocol, digital filters, programmable dividers, control loops for General Purpose A-to-D converters, etc.
• Working on design of Baseband Processor IC. The processor design has 8-way SIMD architecture with custom LIW to support DSP instructions along with AXI bus protocol and peripherals like JTAG, UART, SPI, I2C and I2S.
• Worked on design of digital sections on Transmitter Linearization IC. Digital sections include control FSMs and SPI protocol.
• Area of work includes RTL fixes, synthesis, place and route, timing analysis, logical equivalence, scan insertion and testing.
- Digital IC Design Engineer at Motorola Solutions
- Assistant Systems Engineer at Tata Consultancy Services (TCS)
- Intern at Tata Consultancy Services (TCS)
- Summer Trainee at Bharath Sanchar Nigam Limited
1 year, 8 months at this Job
- Master's - Electrical Engineering
- Bachelor of Technology - Electronics & Communication Engineering
1) Design circuit for the host controller of SD cards used in laptops and cameras by CAD. 2) IC circuit Testing.
- IC Design Engineer at O2 micro
1 year at this Job
- Master's - signal and imaging processing
- Bachelor's - signal and imaging processing
Creation of BSIM4 models for the Global foundries 22nm process for the Xyce simulator using Analog Rails IC Design Platform. Inductor characterization in GF22 GF40 and T16 processes for the Analog Rails IC design Environment. Custom FFT measurements for the Analog Rails IC Design Platform.
- IC Design Engineer at Get2Spec, Inc.
1 month at this Job
- M.S. in Electrical Engineering - Circuits and Systems
o 0.5u 150V SOI: Power on Reset, Analog Buffer, Ring Oscillator, and LDO design. Support Yield enhancements and provide technical expertise on circuit operation. o 0.18u 70V BCD: Operational Amplifiers, design for thermal dissipation, User Programmable inductive voltage clamp.
- Analog IC Design Engineer at Power on Reset
- Systems Engineer at Sean Lofthouse
- Senior Applications Engineer at PROSLIC, Power, and Design
- Senior Applications Engineer at
5 years at this Job
- BS - Analog Design
- MS - Electrical Engineering
Experienced in power system management, reference circuit design, communication protocols (SPI, I2C, CAN, LIN)
● Created simulation regression suite for system verification of a CAN device
● Developed automated validation bench suite for an automotive qualification of a bidirectional I2C buffer using LabView ○ Bench included oscilloscope, power supply, signal generator, thermal stream, EVM
● Led a team to develop a cost reduced LIN System Basis Chip (SBC) for the automotive space on a tight timeline ○ Worked closely with digital design, verification, systems, test, and validation teams to align and provide architectures with full test coverage
- Analog IC Design Engineer at Texas Instruments
- Engineering Technician at Applied Research Labs
- Engineering Intern at Silicon Audio
2 years, 3 months at this Job
- Bachelor of Science - Electrical Engineering
• Working as a Staff ASIC design for HDMI 2.1 transceiver/and SERDES PLL design.
• Working on micro-architectures for Phy/PLL Receiver design
• Work with the ASIC architecture, and PD team to resolve any issues related to ECO, FV, Source Synchronous clock implementation, low power design, and area managements.
- Sr. IC Design Engineer/Architect at Analog Devices Inc & Intel
- Sr. IC Design Engineer IV at Qualcomm
- Sr. Staff IC Design Engineer at AMBA Traffic Generators
- Sr. Staff IC Design Engineer IV at Qualcomm
7 months at this Job
- Ph.D - 1st part
- BSEE - Electronics and Telecommunication
Analog IC IP design in 7nm LP Technology: current reference circuits, voltage reference, a negative capacitance circuit for 60Gbps and/or 112Gbps PCIe Serdes and performed EMIR, self-heating, reliability analysis, and LVS and DRC layout extraction.
● Designed ultra-low power bandgrap (<1uA), voltage and current reference circuits for a medical device in 55nm technology.
● Designing fully-differential baseband transimpedance anti-aliasing filter and a logic frequency divider from 2GHz to 500MHz with 25% duty cycle in 120nm CMOS RF technology.
● Analog IC IP, such as LDO (voltage regulators), and bandgaps for DDR4 PHY integrated circuits with 14nm FinFet Technology, and performed EMIR, self-heating, and LVS and DRC layout extraction.
- Analog IC Design Engineer at ASIC North
- Analog Design Engineer at Toko America Inc
- Design Engineer at Ridgetop Group Inc
- IC Analog Design Engineer, Power Management Team at Motorola Inc
4 years at this Job
- MS - Electrical Engineering
- BS - Electrical and Computer Engineering
Designed working sub-blocks for 5 GHz Frac-N PLL Frequency Synthesizer in 40nm and 55nm CMOS technology, which were part of ARM CORDIO IP (2.4 GHz BLE Transceiver) optimized for LP & ULP process flavors.
• Supply voltage of 975mV and using 32MHz reference frequency.
• Designed and optimized PFDs to have no dead-zone, minimal linearity distortion and efficient frequency detection.
• Worked on Charge pumps with skew compensation to ensure better UP & DN current matching.
• Implemented high speed divider circuits - Divide-by-2 (5GHz → 2.5GHz) and 4/5-Prescaler dividers maintaining proper timing & swing levels across extreme conditions and yield correct divide ratios throughout the tuning range.
• Designed robust biasing circuits, keeping in mind the threshold and device parameter variations across PVT, which resulted in strong correlation between simulated and actual lab measurements.
• Developed opamps/comparators, counters to be used in VCO.
• Ensured all the designs have required proper observability of important circuit outputs and testability in the lab for debugging and collection of performance metrics.
• Responsible for Top-level AMS simulations to ensure PLL locking in extreme conditions.
• Provided guidance to layout engineers, monitored progress & quality and proactively verified layout.
• Adept in Parasitic Extraction (PEX) and made sure simulations are done using correct PEX views and carefully reduced PEX versions wherever applicable to improve the simulation time.
• Experience in extracting DSPF (Detailed Standard Parasitic Format) files using Voltus-Fi to check for EMIR compliance of designs for reliability at extreme conditions.
- Analog IC Design Engineer at ARM Pvt Ltd
- Masters Technical Intern (Analog & Mixed-Signal Design) at Broadcom Corporation
2 years, 7 months at this Job
- Master of Engineering in Electrical Engineering - Electrical Engineering
- Bachelor's - Electronics & Comm. Engineering
Microsoft, 1065 La Avenida, Mountain View CA 94043 July, 2013 - October 2013 (CWF) Analog IC design engineer consultant Responsible for design, validation cross check of previously developed and/or nearly completed blocks and simulation of top level features supporting a laser based application. Simulations performed use a combination of customized in-house tools consisting of schematic capture and net-list formats. Design and cross check tasks are required to meet design specifications over typical and PVT requirements after parasitic extraction is completed. Continuous communication with design and recording of results in report format with team members runs in parallel with simulations tasks. Additional responsibilities includes supporting design reviews and status reports as required.
- Analog IC design engineer consultant at
- CWF / Contractor Work Force at Intel
- Senior RF at Freescale SemiConductor
- IC Design Consultant supporting Corporate R &D (Contractor opportunity) at TahoeRF
3 months at this Job
- Master of Science - Electrical Engineering
- Bachelor of Science - Physics Research
Creating and implementing solutions for ASIC and SoC products from concept and specification through architecture to silicon realization and system level application and test.
• Analog high speed CMOS design and physical implementation (inc. low power, low voltage)
• Specialist in the architecture, floorplanning and implementation of high speed, wide bandwidth I/O interfaces for High Performance Computing/Supercomputer/Server chips
• High Speed Memory & Serial Interface design and integration - DDRx, GDDR5, PCIe 1/2/3
• Power Distribution Network (PDN) design and Power Supply Noise (PSN) reduction
• Expertise in Signal Integrity (SI) and Power Integrity (PI) at chip, package and board level
• Strong in Tools, Flows and Methods (TFM) for deep sub-micron and nanometer technologies
• Extensive experience in System-on-Chip (SoC) designs
• Proficient in Design For Manufacturing (DFM)
• Laboratory characterization, analysis and debugging
• Experienced in cross-functional and multi-disciplinary teams (inc. package and board design)
• RF/Microwave measurement and modeling experience for devices and circuits up to 60 GHz
- Semiconductor Analog IC Design and Implementation Consultant at Davies Consulting
- Staff Analog Design Engineer at Intel Corporation
- Principal Engineer, Corporate Applications at Rambus Inc
- Staff Design Engineer at Lattice Semiconductor Corporation
11 years at this Job
- Ph.D. - Electrical Engineering
- BSc. - Electrical and Electronic Engineering