- senior physical design engineer at Synapse Design
12 years, 3 months at this Job
Implemented layout of low power Oscillator IP including top level floorplan, power grid generation, placement of thin gate
transistors, large resistors and capacitors array using Cadence Modgen Utility, routing and signoff verification checks. Utilized
FDK track patterns to ensure all the layers are on grid.
• Completed layouts of high speed application blocks (Sampler) for both 14nm and 7nm. Implemented layouts with compact aspect ratio using cut metals, tap cells creation as well as symmetrical, matched routing to meet design specs.
• Carefully planned, coordinated daily progress with DE and abroad teams for delivering LDO layouts on time based on aggressive schedule. Delivered matching critical shared blocks with shielding, common OD and identical dummy requirements. Took care of most of the top level hook up including 5000 mfccaps and fixed critical LVS/DRC/Antenna DRC/Density errors.
• Worked on mixed signal IPs which required many iterations with respect to design/layout changes to achieve best performance. Contributed on all the sub hierarchy cells to work on top level design. Challenges involved while performing ECOs on flattened custom digital standard cell layouts which is not XL compliant.
• Generated abstracts/LEFs manually and using cadence abstract generator for many IPs on 5nm, 7nm process nodes for Early View and Final View drops to SOC team.
• Widely recognized for demonstrating quality of work and high level of performance on a competitive schedule, driving issues to closer, timely deliverables, willingness to share solutions with the team and mentor other colleagues on gained expertise.
- Physical Design Engineer at Intel Corporation
- Associate Member of Technical Staff at Tezzaron Semiconductor
- Research Assistant at Southern Illinois University Edwardsville (SIUE)
2 years, 4 months at this Job
- Master of Science - Electrical and Computer Engineering
- Bachelor of Engineering - Electrical Engineering
Roles and Responsibilities
• Worked in Advanced Design Group of Logic Technology Development team that delivers critical circuits in advanced CMOS technologies.
• Delivered Analog/Digital/Memory layouts with a particular focus on improving productivity.
• Created bottoms-up elements of chip-design in advanced CMOS technologies that included standard library cell components.
• Designed analog collateral device templates for process characterization.
• Worked on creation, maintenance, and distribution of DR clean template (primary elements of chip design) library IP across the organization as and when necessary.
• Drove RTL-to-layout synthesis and Place&Route flows, and performed cleanup needed.
• Optimized physical design methodology and streamlined work flows that enabled high productivity and efficiency for the organization by performing problem exploration, feasibility studies and establishing/implementing recommendations made by design automation teams.
• Developed code to maintain layout automation features and macros in layout entry tools to improve layout quality and productivity qualifications. Physical Design Engineering
• Created and maintained physical layouts of bottoms-up elements of chip-design in advanced CMOS technologies of 22nm and 14nm which includes various basic analog electronic components like capacitors, resistors, inductors, varactors, thermal diodes, clamps, decaps etc., and also standard digital library cell components such as logic gates.
• Worked on cell and block-level custom layouts, FUB-level floor plans, abstract view generation schematic-to-layout verification and debug on the layouts using all phases of physical design development including custom polygon editing, auto-place and route algorithms, floor planning, full-chip assembly and other system level routines within a customized physical design framework.
• Worked through successful tape-ins of various test-chips and SRAM chips of 22nm and 14nm processes.
• Worked to provide analog collateral device template IP for 22nm processor teams like IVB (Ivy Bridge), HSW (Haswell) and 14nm processor teams like Broadwell and Skylake.
• Used various internal and external EDA tools for development, implementation and validation of physical layouts.
• Performed data-sanctity checks by running various verification flows like DRC, LVS, TRC, ERC, XOR, RV, DFT/ DFM check, Density check, Carmel (parasitic extraction) on libraries and reported all the errors. Maintenance included revision and clean-up of the physical layouts with every DR runset, UPF and requirement updates.
• Collected data from various teams about their requisitions on the libraries and created EAM page that enables/controls read&write access to all the working members (including mask designers, design engineers and physical design engineers).
• Ensured a smooth working environment for mask designers by providing setup, installing runset updates as and when available in the design environment.
• Developed Perl/Tcl scripts to handle various requirements of data manipulation and reporting.
• Wrote macros for layout synthesis tool that helped in automating the user-specific tasks. Library Releases
• Conducted template library releases at regular intervals to provide HIP to various teams within AD (Advanced Design) as well as external teams such as ASDG (Atom and SOC Development Group) and IAG (Intel Architecture Group).
• Worked as primary point of contact for analog template libraries of 22nm (both CPU and SoC dot process technologies) and ensured clean and timely library releases
• Library release checklist included o Collecting inputs from teams across Intel that used template libraries for recommendations and changes in layout and delivering them within the stipulated time. o Ensuring data-sanctity while providing IP to various teams of different dot process technologies by running central layout regression tool on the entire library. o Checking data in and out of data-sync, tagging data and maintaining version control of the libraries. o Creating and running various scripts using Perl and Tcl that helped in automation of the otherwise elaborate lengthy process. o Creating and maintaining proper documentation for the entire library as well as subsequent releases using release notes.
- Physical Design Engineer / Design Automation Engineer at Intel Corporation
- Photonics Systems Development Lab at University of Cincinnati
- at National Small Industries Corporation
2 years at this Job
- Masters - Computer Engineering
- Bachelors - Electronics and Comm. Engineering
Total 15 years of experience in floor plan, place & route, clock tree synthesis, static timing closure, signal integrity closure & physical verification of designs using Synopys ICC2, INNOVUS tools. Worked on latest technologies like 90, 65, 45, 28, 20 16, 14 and 7nm
Total 15 years of experience in floor plan, place & route, clock tree synthesis, static timing closure, signal
integrity closure & physical verification of designs using Synopys ICC2, INNOVUS tools. Worked on
latest technologies like 90, 65, 45, 28, 20 16, 14 and 7nm
- Physical Design Engineer at Qualcomm
2 years, 4 months at this Job
- MS - VLSI CAD
- Bachelor of Engineering - Instrumentation
• Designed and performed physical block integration of 4 new Register Files in 14nm FinFET for Intel Atom low power processor. Design were taped out and function on Silicon.
• Mapping the designed register files to 10nm FinFET technology.
• Using Intel Integration Flow for Floorplanning. Placement and Route using Intel placement and route.
• Performed Static Timing Analysis (STA) with Intel internal STA tool. Margin Check across process corners and backend design signoff closures such as Noise, EM/IR analysis. Ran LVS/DRC verification.
• Perform check on the slack timing report. Fixed all the timing violation path and redo backend checks.
• Delivered 75 new standard cells for 10nm FinFet circuit library.
• Ran full characterization on the library cells to ensure they are compliant to the library flow and requirements.
- Array Circuit Design / Physical Design Engineer at INTEL CORPORATION
- Member of Technical Staff, Library and Memory Group at FREESCALE SEMICONDUCTOR
- SRAM Circuit Design Engineer, Embedded Memory Development Group at TEXAS INSTRUMENT INC
- Circuit Design Engineer at MOTOROLA INC
2 years at this Job
- Master of Science (M.S) in Electrical Engineering - Electrical Engineering
- Bachelor of Science - Electrical Engineering
Hold 2 years, 2 months of experience along with training in SoCtronics.
- Physical Design Engineer at Soctronics
2 years, 2 months at this Job
- Certification - Technology
Layout Integration for chipsets, graphics, display, and memory IP.
- Physical Design Engineer at Intel Corp.
- Bradley Mechanic at US Army
18 years, 3 months at this Job
- BS - Electronics Engineering Technology
APR Implementation for Cable Modem Product
• Owned a complex block, with 1.2M place-able instances including critical clocking units, from floorplan to tape-out
• Designed a custom power-grid on top of Level-shifters to solve IR-drop issues
• Designed custom H-network from PLL to the Dividers in top-level metals
• Implemented logical ECOs and performed FEV, DRC, DEN, LVS closure to Tape-IN.
• Performed major bug fixes with multi-partition metal-only stepping APR Implementation for Smartphone Product
• Synthesized a large block with 800K+ place-able instances on Intel 14nm technology with voltage areas
• Executed APR in ICC2 using UPF, with 3 switched power domains and one AON power domain
• Ran Formal Equivalence Verification (FEV) and provided feedback to RTL team on failures & ways to solve them
• Checked for Voltage Domain crossings using Spyglass and provided feedback to the RTL team regarding UPF issues. Scripting
• Wrote TCL script to find overlaps in a FILL DB & enhanced it to provide various options for users
• Coded TCL script to move a cell to the center of its fan-out iteratively & eventually reduced runtime from 1hr to 7mins.
- Physical Design Engineer at Intel Corporation
- Hardware Engineer at Qualcomm Inc
- Hardware Intern at Broadcom Corporation
4 years, 7 months at this Job
- MS - Electrical Engineering
- BE - Electronics & Communication Engineering
o Lead project physical design activities (block and top-level) from netlist to GDS, including floorplan, place and route, CTS, and sign-off STA/IREM/PV checks o Make project schedules, identify project issues, and cooperate with different teams (e.g. RTL, synchesis, DFT, package, IP/lib teams) to ensure timely and quality project execution. o Drive for solutions of critical technical issues, e.g. floorplan change, timing closure, IR hotspot o Plan for new projects, new technology assessment, working with IP vendors on IP requirements and implementation guidelines, working with EDA vendors on PD flow development and enhancement o Deep dive into key technologies in high performance CPU core design, such as AVFS, clock mesh, power network, synthesis/PR optimizations. o Successfully taped-out multiple high-performance CPU chips with 14nm technology
- Director/Principal Engineer of Physical Design at HARC
- Senior Member of Technical Staff at AMD
- Senior Physical Design Engineer at Intel
- Research Assistant at University of Rochester
3 years, 5 months at this Job
- Ph.D. in ECE - ECE
- M.S. in EE - EE
- B.S. in EE - EE
Responsibilities At apple headquarters, worked on upcoming Apple A9 chips for iphone. Full chip physical verification Closely interacted with packaging team and SoC integration team for Padring design and Bump/RDL layer design. SoC Physical Verification including DRC, LVS, DFM rule checks Provide early feedback to the place and route team on fixing DRCs Familiar with identifying fixes for complex DRC rules in 28nm and lower nodes Strong Debug capabilities to resolve LVS issues
- Physical Verification Engineer at Apple Inc
- Sr Physical Design Engineer at Smartplay Inc
- Staff member PD at SmartPlay
- Senior Engineer R&D Services at MindTree Consulting
6 years, 1 month at this Job
- M. Tech - VLSI
- BE - Electronics and communication